Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Kao Corporation

Jun Deguchi

Daisuke Miyashita

Shouhei Kousai

Hiroyuki Kobayashi

Junji Wadatsumi

Makoto Morimoto

Naoki Kobayashi

Hideaki Majima

Daiki Ono

Fumihiko Tachibana

Takashi Toi

Takao Marukame

Yoshifumi Nishi

Masamichi Suzuki

Toshiyuki Yamagishi

Yuji Satoh

Yuta Tsubouchi

Radu Berdan

Makoto Sakakibara

Daichi Sakoda

Nau Ozaki

Haruki Toda

Yoshinori Suzuki

Tamio Ikehashi

Atsuhiro Kinoshita

Atsushi Kawasumi

Naofumi Nakamura

Toshimasa Namekawa

Tetsufumi Tanamoto

Yuichi Nakamura

Shinji Miyano

Yuichiro Mitani

Hidehiro Shiga

Kei Masunishi

Ichiro Seto

Masahiro Sekiya

Koji Horisaki

Yumi Hayashi

Keiji Endo

Yukiyasu Tatsuzawa

Shinichi Sasaki

Yousuke Hagiwara

Yusaku Asano

Yuki Fujimura

Kazuhiro Hiwada

Tatsuji Ashitani

Hisao Kawasato

Motohiro Morisaki

Hideyuki Kokatsu

Asuka Maki

Kengo Nakata

Hideki Yamada

Shoko Oda

Yasuto Hoshi

Mai Suetsugu

Teruhisa Fujimatsu

According to one embodiment, an information processing method includes: calculating a first feature amount of query data in a first field; calculating first similarity degrees between the first feature amount and second feature amounts in the first field; obtaining, based on the first similarity degrees, third feature amounts in a second field that are associated with feature amounts selected from the second feature amounts, the second field being different from the first field; calculating fourth feature amounts in the second field, for choices concerning the query data; calculating second similarity degrees between the third feature amounts and the fourth feature amounts; and selecting, based on the second similarity degrees, an answer to the query data among answer candidates corresponding to the third feature amounts.

Information processing method, information processing device, and computer system

According to one embodiment, in a semiconductor integrated circuit, a second switch has a first end connected to a first end of a capacitive element and a second end connected to a node of a reference potential. A third switch has a first end connected to the first end of the capacitive element and a second end connected to an input node of an amplifier circuit. A control circuit maintains the second switch in an on state while maintaining a first and the third switches in an off state in a first period and maintains the first switch in an on state while maintaining the second and third switches in an off state in a second period after the first period. End timings of the second period in the plurality of DA converters are synchronized with each other in response to a signal from a global circuit.

Semiconductor integrated circuit and arithmetic system

According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.

Computation system with a plurality of comparators and a global circuit

To provide a method for predicting a soybean yield at an early stage with high accuracy. The method for predicting a soybean yield comprises: acquiring analytical data of one or more components from a leaf sample collected from the soybean; and predicting a soybean yield using a correlation between the data and a soybean yield.

Method of predicting soybean yield

A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

Semiconductor storage device

According to one embodiment, an information processing device includes: an encoder including a first layer and a second layer which are coupled in series; and a decoder. The encoder is configured to: generate, based on first data, a first key and a first value in the first layer, and a second key and a second value in the second layer; and generate, based on second data different from the first data, a first query in the first layer, and a second query in the second layer. The decoder is configured to: generate third data which is included in the first data and is not included in the second data, based on the first key, the first value, the first query, the second key, the second value, and the second query.

Information processing device, information processing method, and generating method of learning model

Provided is a method with which an &#x3b1;-allylated cycloalkanone is obtained from a macroyclic compound used as a starting material. The method is a method for producing an &#x3b1;-allylated cycloalkanone represented by General Formula (IV), and the method includes a step of reacting a compound represented by General Formula (I) and/or a compound represented by General Formula (II) with a compound represented by General Formula (III) in the presence of an acid catalyst to produce an &#x3b1;-allylated cycloalkanone represented by General Formula (IV), the acid catalyst including an acid catalyst that includes an ammonium cation and an anion. where R, R, and Rare the same or different and each of them is an alky group having 1 or mom and 4 or less of carbon atoms, the group -A- (it should be noted that the front bond refers to a bond that binds to the carbon atom Cand the back bond refers to a bond that binds to the carbon atom C) is an alkylene group having 4 or more and 20 or les of carbon atoms that optionally contains a hetero atom and optionally has a substituent, and Ris a hydrogen atom or an alkyl group having 1 or more and 4 or less of carbon atoms.

Method for producing &#x3b1;-allylated cycloalkanone

Provided is a method with which an &#x3b1;-allylated cycloalkanone is obtained from a cyclic compound cycloalkanone used as a starting material. The method is a method for producing an &#x3b1;-allylated cycloalkanone represented by General Formula (III), and the method includes: a step 1: reacting a compound represented by General Formula (I) and alcohol having 1 or more and 4 or less of carbon atoms in the presence of a first acid catalyst and optionally a dehydrating agent; and a step 2: reacting a crude product obtained in the step 1 and a compound represented by General Formula (II) in the presence of a second acid catalyst to produce an &#x3b1;-allylated cycloalkanone represented by General Formula (III). The step 1 and the step 2 are consecutively performed. In the formulae above, the group -A- (it should be noted that the front bond refers to a bond that binds to the carbon atom Cand the back bond refers to a bond that binds to the carbon atom C) is an alkylene group having 4 or more and 20 or less of carbon atoms that optionally contains a hetero atom and optionally has a substituent, and Ris a hydrogen atom or an alkyl group having 1 or more and 4 or less of carbon atoms.

Method for producing alpha-allylated cycloalkanone

A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.

Memory system including multiple memories connected in series

According to an embodiment, a quantum annealing apparatus includes: an output unit acquiring and outputting components in a Z axis from a plurality of quantum bits in a quantum calculation; and an operation unit executes: a selecting process of selecting a first quantum bit, a second quantum bit and a third quantum bit, the second quantum bit and the third quantum bit being coupled in the quantum calculation unit; a first rotating operation of rotating each of the second quantum bit and the third quantum bit by 90&#xb0; around a first axis perpendicular to the Z axis; an interaction operation of causing the first quantum bit and the second quantum bit to interact with each other; and a second rotating operation of rotating each of the second quantum bit and the third quantum bit by 90&#xb0; around a second axis perpendicular to the Z axis and the first axis.

Quantum annealing apparatus

According to one embodiment, a semiconductor memory device includes a memory, a controller, and a sense amplifier. The memory includes a plurality of memory cells, wherein each of the memory cells can store a multi level indicating one data. The controller writes the multi level to one cell of the memory. The sense amplifier performs unary read of data from the multi level written in the one cell. The data is data in which an error of a predetermined lower significant bit is allowed. The controller reads data indicated by the multi level stored in the one cell of the memory from the sense amplifier.

Semiconductor memory device

According to one embodiment, in a reception apparatus, a reception node is capable of being connected to a wired communication channel. A first frequency conversion circuit is electrically connected to the reception node. A second frequency conversion circuit is electrically connected to the reception node. A first adder circuit is electrically connected to the first frequency conversion circuit. A second adder circuit is electrically connected to the second frequency conversion circuit. A first correction circuit is electrically connected between the first frequency conversion circuit and the second adder circuit. A second correction circuit is electrically connected between the second frequency conversion circuit and the first adder circuit. The first correction circuit includes a reverse phase amplifier and a first capacitative element. The second correction circuit includes a positive phase amplifier and a second capacitative element.

Reception apparatus, transmission apparatus, and communication system

According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.

Transmitter and receiver

A memcapacitor according to an embodiment includes a first electrode, a first dielectric layer provided on the first electrode, a plurality of variable resistance portions provided separately from each other on the first dielectric layer, a second dielectric layer provided on the first dielectric layer and between the variable resistance portions, and a second electrode provided on the variable resistance portions and the second dielectric layer. Each of the variable resistance portions is formed of a material that allows diffusion of metal atoms constituting the second electrode to inside of the variable resistance portion, and the second dielectric layer is formed of a material that prevents diffusion of the metal atoms constituting the second electrode to inside of the second dielectric layer.

Memcapacitor, neuro device, and neural network device

Growing community of inventors

Kawasaki, Japan

Jun Deguchi