Yangtze Memory Technologies Co., Ltd.

Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

Guangzhou Sunmile Dynamic Technologies Corp., Ltd

Seb S.a.

Xi'an Jiaotong University

State Grid Corporation of China

Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.

Accelink Technologies Co., Ltd.

China Electric Power Research Institute

State Grid Hubei Electric Power Research Institute

Naval University of Engineering

Wuhan Titum Motor Technology Co., Ltd

Wuhan Eoptics Technology Co., Ltd.

Shenzhen Joint Technology Co., Ltd

Wuhan Ttium Motor Technology Co., Ltd.

Jun Chen

Zhenyu Lu

Jifeng Zhu

Qian Tao

Yushi Hu

Li Hong Xiao

Si Ping Hu

Simon Shi-Ning Yang

Steve Weiyi Yang

Xiaowang Dai

Jin Wen Dong

Lan Yao

Haohao Yang

Zi Qun Hua

Zhiliang Xia

Weihua Cheng

Kun Bao

Yu Huang

A Man Zheng

Zongliang Huo

Guanping Wu

Wenguang Shi

Feng Pan

Jia Wen Wang

Zhong Zhang

Ji Xia

Yu Ting Zhou

Tao Wang

Zhao Hui Tang

Zhaosong Li

Sizhe Li

Shi Qi Huang

Yue Qiang Pu

Yan Ni Li

Yu Long Wang

Fuhai Duan

Jun Liu

Meng Wang

Lidong Song

Yongna Li

LongDong Liu

Chao Chen

Liang Sun

Lei Zhang

Guang Li

Jun Li

Shuai Yuan

Chengpeng Fu

Shiyuan Liu

Hao Wang

Chunping Yu

Yuan Lin Yang

Jintao Tao

Xiuguo Chen

He Chen

Hui Li

Jin Lyu

Menghui Le

Chaoyu Yuan

Jiangang Bi

Shou-Cheng Wang

Shaoning Mei

Jun Lu

Junhao Li

Jinghui Chen

Steve Wiyi Yang

Fan Liu

Yanming Li

Lianghong Wu

Jianfeng Liang

Kunfeng Li

Zunyan Chen

Haiqiong Liu

Jinbin Li

Yi Sheng Qu

Ji Qiang Fu

Yang Fu

Liang Mei

Zichun Yang

Guobing Chen

Feiyue Yang

Shuang Zhao

Zhifang Fei

Wencai Sun

A memory device includes an alternating layer stack including conductive/dielectric layer pairs stacked in a first direction, a first insulating layer on the alternating layer stack, a thickness of the first insulating layer being larger than a thickness of the dielectric layer, and a channel structure extending through the alternating layer stack and the first insulating layer along the first direction. The channel structure includes an epitaxial layer disposed at a first end of the channel structure away from the first insulating layer, a functional layer on the epitaxial layer and extending along the first direction, a channel layer covering a sidewall of the functional layer and in contact with the epitaxial layer, and a filling structure covering a sidewall of the channel layer. The memory device further includes a channel column structure at a second end of the channel structure near the first insulating layer and in contact with the channel layer, and a top selective gate structure over the first insulating layer and between neighboring channel column structures.

Three-dimensional memory devices and fabricating methods thereof

Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The method comprises forming an array device semiconductor structure comprising an alternating conductor/dielectric stack disposed on a semiconductor layer, and an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The method further comprises a peripheral device disposed on a substrate, and a peripheral interconnect layer disposed on the peripheral device and including a second interconnect structure and a pad. The pad is electrically connected with the peripheral device through the second interconnect structure. The method further comprises bonding the array interconnect layer to the peripheral interconnect layer, such that the first interconnect structure is joined with the second interconnect structure. The method further comprises forming a pad opening exposing a surface of the pad.

Embedded pad structures of three-dimensional memory devices and fabrication methods thereof

A three-dimensional (3D) NAND memory device includes a substrate, a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack to the substrate. The first stack is disposed on the substrate and includes first and second dielectric layers arranged alternately in a vertical direction. The second stack is disposed on the substrate and includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure has an unclosed shape.

Hybrid bonding contact structure of three-dimensional memory device

A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Staircase structure for memory device

Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.

Memory cell structure of a three-dimensional memory device

An organic light-emitting diode display panel is disclosed. By using four display panels sequentially disposed in a stack arrangement from top to bottom, light emitted in a same direction from each of the display panels, and subpixels of the four display panels not overlapping one another, a screen resolution of the organic light-emitting diode display panel can increase by three times without increasing pixel density of masks or density of array layers.

Organic light-emitting diode display panel

The disclosure is an intelligent electronic lock. The intelligent electronic lock includes: an electronic lock shell, a wireless communication module, an instruction input device, the instruction input device is arranged on the electronic lock shell for instruction input, a processor, the processor is connected to the wireless communication module and the instruction input device is connected to receive and send signals, and the electronic rope.

Intelligent electronic lock

A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.

Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.

Method for forming channel hole plug of three-dimensional memory device

Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.

Three-dimensional memory devices and methods for forming the same

Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.

Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof

Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure including two parallel barrier walls extending vertically through the alternating layer stack and laterally along a word line direction to laterally separate the first region from the second region. The memory device further comprises a plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack.

Embodiments of three-dimensional (3D) memory devices having a shielding layer and methods for forming the 3D memory devices are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral device is formed on a first substrate. A first interconnect layer including first interconnect structures are formed above the peripheral device on the first substrate. A shielding layer including a conduction region is formed above the first interconnect layer on the first substrate. The conduction region of the shielding layer covers substantially an area of the first interconnect structures in the first interconnect layer. An alternating conductor/dielectric stack and memory strings each extending vertically through the alternating conductor/dielectric stack are formed on a second substrate. A second interconnect layer including second interconnect structures is formed above the plurality of memory strings on the second substrate. The first substrate and the second substrate are bonded in a face-to-face manner, such that the shielding layer is between the first interconnect layer and the second interconnect layer.

Three-dimensional memory device having a shielding layer and method for forming the same

A three-dimensional (3D) memory device includes a peripheral device, a plurality of memory strings, a layer between the peripheral device and the plurality of memory strings, and a contact. The layer includes a conduction region and an isolation region. The contact extends through the isolation region of the layer.

Growing community of inventors

Hubei, China

Jun Chen