Tusimple, Inc.

Qualcomm Incorporated

Jun Chen

Liu Liu

Wutu Lin

Zijie Xuan

Arda Kurt

Yujia Wu

Haoming Sun

Aaron Havens

Yangyang Sun

Shiqun Gu

Stanley Seungchul Song

Junjing Bao

Choh Fei Yeap

Vidhya Ramachandran

Jeffrey Xu

John Jianhong Zhu

Ye Lu

Giridhar Nallapati

Lixin Ge

Dongming He

Kwanyong Lim

Jihong Choi

Lily Zhao

Christine Sung-An Hau-Riege

Ahmer Syed

Disclosed are techniques for integrated circuit device. In an aspect, an integrated circuit device includes a metallization structure that includes a top metal layer structure; a passivation layer on the metallization structure; a bump structure disposed on the first bump line structure; and a first polymer protection layer. The passivation layer may include one or more first openings. The first bump line structure may include one or more first extended portions respectively extending toward the top metal layer structure through the one or more first openings. The bump structure may be electrically coupled to the first bump line structure. The first polymer protection layer may be on the passivation layer, on a portion of the first bump line structure, and in contact with a side surface of the first bump line structure.

Flip-chip bumping metal layer and bump structure

Systems and methods for dynamic predictive control of autonomous vehicles are disclosed. In one aspect, an in-vehicle control system for a semi-truck includes one or more control mechanisms configured to control movement of the semi-truck and a processor. The system further includes computer-readable memory in communication with the processor and having stored thereon computer-executable instructions to cause the processor to receive a desired trajectory and a vehicle status of the semi-truck, determine a dynamic model of the semi-truck based on the desired trajectory and the vehicle status, determine at least one quadratic program (QP) problem based on the dynamic model, generate at least one control command for controlling the semi-truck by solving the at least one QP problem, and provide the at least one control command to the one or more control mechanisms.

Systems and methods for dynamic predictive control of autonomous vehicles

A system and method for implementing a neural network based vehicle dynamics model are disclosed. A particular embodiment includes: training a machine learning system with a training dataset corresponding to a desired autonomous vehicle simulation environment; receiving vehicle control command data and vehicle status data, the vehicle control command data not including vehicle component types or characteristics of a specific vehicle; by use of the trained machine learning system, the vehicle control command data, and vehicle status data, generating simulated vehicle dynamics data including predicted vehicle acceleration data; providing the simulated vehicle dynamics data to an autonomous vehicle simulation system implementing the autonomous vehicle simulation environment; and using data produced by the autonomous vehicle simulation system to modify the vehicle status data for a subsequent iteration.

Neural network based vehicle dynamics model

3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.

Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) electrically coupled by integrated vertical FET-to-FET interconnects for complementary metal-oxide semiconductor (CMOS) cell circuits

Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a substrate, a first group of metal layers including a plurality of first fingers over the substrate, wherein the first fingers are formed without a via. The integrated circuit may further include a second group of metal layers including a plurality of second fingers over the first group of metal layers, wherein the second fingers are formed with vias, and wherein the first and the second group of metal layers are formed by a processing technology node of 7 nm or below.

High density and reliable vertical natural capacitors

Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

Systems and methods to reduce parasitic capacitance

Growing community of inventors

San Diego, CA, United States of America

Jun Chen