Texas Instruments Corporation

Jun Chen

Siew Kuok Hoon

Franco Maloberti

David W Evans

James L Krug

Valerian Mayega

Xiaoyu Xi

Keith Edmund Kunz

Norman L Culp

Jian Zhou

SiewKuok Hoon

A switching regulation system and control scheme efficiently enables driving multiple loads from a common energy storage element, such as an inductor. The control scheme operates to store energy in the energy storage element over a first portion of a cycle, such as by ramping up current through an inductor, according to energy requirements of the multiple loads. After storing the energy in the storage element during the first portion of the cycle, the stored energy is delivered consecutively to each of the multiple loads over a subsequent portion of the cycle.

DC/DC power converter

A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state to couple the output node with the input supply node and non-conductive state according to cooperative operation of a second transistor and a third transistor. The second transistor is coupled to provide a control input to drive the first transistor to the conductive state thereof in response a first input signal provided at a control input of the second transistor. The third transistor is coupled to provide an output at the output node in response to a second input signal provided at a control input of the third transistor, the first and second input signals being out of phase with each other. Circuitry is coupled between the input supply node and the control input of the first transistor to provide reduced impedance at the control input of the first transistor according to operation of the second transistor.

Driver circuit

A single-inductor dual-output buck converter facilitates power conversion by converting a single DC power source/supply into two separate DC outputs, each of which can be configured to provide a selected/desired voltage. The converter includes a single inductor and three power switches, which control operation of the converter. The converter has four basic stages of operation in which power is initially supplied to a first output that also stores charge. Subsequently, the stored charge of the first output is employed to provide power to a second output.

Single inductor dual output buck converter

A single-inductor dual-output buck converter and control method that facilitates power conversion by converting a single DC power source/supply into two separate DC outputs, each of which can be configured to provide a selected/desired voltage by selection of respective duty cycles. The topology of the inverter includes a pair of diodes or switches that can selectively re-circulate inductor current. The converter is generally operated at a fixed frequency with four stages of operation. A first and third stage of operation provide power to a first and second output, respectively. A second and fourth stage of operation re-circulate inductor current and can partially recharge a battery type power source. The power output for each stage (voltage and current) can be selectively obtained by computing and employing appropriate time periods for the stages of operation that correspond to appropriate duty cycles.

Single inductor dual output buck converter with frequency and time varying offset control

The present invention provides improved line and load regulation of a switching-mode power converter () without requiring additional capacitors (), either internally or externally, to stabilize the control loop. The present invention can provide this by integrating a digital compensator () with the pulse-width modulator ('PWM') of the switching-mode power converter. Such a compensator () can include comparators (and), digital circuits (), and resistors (, and).

Switching mode power conversion with digital compensation

The frequency doubling circuit and method provides an output signal with stable frequency and a 50% duty cycle. The frequency of the output signal is two times a frequency of the input signal. The circuit only requires four comparators, eight small capacitors, and some switches and transistors for frequency doubling applications. With the help of feedforward structure, the circuit has an almost-instantaneous response. The performance of the provided frequency doubling circuit and method is independent of the frequency and duty cycle of input signal, power supply voltage, temperature, and process variations.

Compact frequency doubler/multiplier circuitry

System for a current source with enhanced output impedance. A preferred embodiment comprises a cascode current source arranged in a current mirror configuration (such as current source) with a pair of level shifters arranged in a source-follower configuration (such as level shiftersand). The level shifters reduce the compliance voltage of the current source, permitting use in low voltage applications.

Regulated cascode current source with wide output swing

A low drop-out voltage regulator uses a voltage subtractor circuitto form a power supply rejection boost circuit. The voltage subtractoris inserted between the pass elementand the amplifierof the low drop-out regulator. The voltage regulator circuit includes a pass elementcoupled between an input node and an output node; a voltage feedback circuitandcoupled to the output node Vo; an amplifierhaving an input coupled to the voltage feedback circuit; and a voltage subtractorhaving a control node coupled to an output of the amplifier, an output coupled to a control node of the pass element, and an input coupled to the input node. The boost circuit improves supply noise rejection performance significantly without adding much complexity to the regulator system. The boost circuit is simple and consumes negligible silicon area and power.

Low drop-out voltage regulator with power supply rejection boost circuit

A threshold voltage extraction circuit. The circuit includes a first current mirror having a first transistor and a second transistor. A holding circuit has an output adapted to control a current though the first current mirror by operating to maintain substantially equal the voltages at a first input thereof and at a second input thereof. A third, MOS transistor having a source and a gate, and a resistor circuit, together adapted to generate a voltage which is a multiple of a source-gate threshold voltage of the third transistor, are coupled to the second transistor and to the first input of the holding circuit. A fourth, MOS transistor coupled to the first transistor and to the second input of the subtracting circuit through a second resistor circuit is adapted to generate a threshold voltage across the second resistor circuit, by the operation of the holding circuit. A second current mirror coupled to the first current mirror is adapted to cause a current to flow through a third resistor circuit that corresponds to the current through the first current mirror to thereby provide an output voltage corresponding to the threshold voltage.

Threshold voltage extraction circuit

A bandgap reference circuit. The circuit includes a first current mirror having a first mirror transistor and a second mirror transistor. A holding circuit has an output adapted to control a current though the first current mirror by operating to maintain substantially equal the voltages at a first input thereof and at a second input thereof. A first bipolar transistor having an emitter, a base, and a collector, wherein the area of the emitter thereof has a predetermined size, is arranged to conduct a collector current from the first mirror transistor. A second bipolar transistor having an emitter, a base, and a collector, wherein the area of the emitter thereof has a size that is proportional to the size of the emitter area of the first bipolar transistor, is arranged to conduct a collector current from the second mirror transistor, the base thereof being connected to the collector thereof. A first resistor is provided, in series with the collector of the second bipolar transistor and the second mirror transistor. The base of the first bipolar transistor is coupled to a common connection node of the first resistor and the second mirror transistor to substantially reduce the effects of offset error in the holding circuit. The holding circuit may be an operational amplifier.

Bandgap voltage reference insensitive to voltage offset

The low dropout voltage regulator (LDO) circuit with improved power supply rejection ratio includes: a first amplifier having a first input coupled to a reference voltage node V ; a second amplifier having an input coupled to an output of the first amplifier ; a pass transistor having a control node coupled to an output of the second amplifier ; a feedback circuit and having an input coupled to the pass transistor and an output coupled to a second input of the first amplifier ; an inverting gain stage coupled to the input of the second amplifier ; and a high pass filter , and coupled between a power supply node and a control node of the inverting gain stage . The circuit uses the high pass filter , and and inverting gain stage to feedforward the power supply ripple into the LDO's control loop which counter-acts the impact of the supply ripple on the output node V .

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Allen, TX, United States of America

Jun Chen