Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP (Singapore) Pte. Ltd.

Other

Jun Cao

Afshin Momtaz

Delong Cui

Ali Nazemi

Adesh Garg

Brandon Carl Smith

Armond Hairapetian

Anand Jitendra Vasani

Guangming Yin

Guansheng Li

William Dai

Yong Liu

Xin Wang

David Chung

Jiawen Zhang

Namik Kocaman

Bo Zhang

Ahmed Elkholy

Heng Zhang

Siavash Fallahi

Chung-Jue Chen

Mohammad Nejad

Meisam Honarvar Nazari

Burak Catli

Tim Yee He

Chang Liu

Ali Ghiasi

David N Wong

Tamer Mohammed Ali

Vivek Telang

Cheng-Chung Shih

Ullas Singh

Yao-Ching Liu

Jason Chao

Bharath Raghavan

Yonghyun Shim

Eric Ng

Hyo Gyuem Rhew

Kun Chuai

Zhiyu Ru

Vasudevan Parthasarathy

Kang Xiao

Mehdi Khanpour

Seong-Ho Lee

Wei Zhang

Hong Chen

Yousr Ismail

Alireza Nilchi

Hyung-Joon Jeon

Mohammadamin Torabi

Mehmet Batuhan Dayanik

YU-Ming Ying

Kangmin Hu

Lakshmi Rao

Kuo-J Huang

Ramon Alejandro Gomez

Yongbum Kim

Jan Mulder

Jan Roelof Westra

Hongtao Jiang

Zhongfeng Wang

Kambiz Vakilian

Iuri Mehr

Mahmoud Reza Ahmadi

Arvindh Iyer

SangHye Chung

Derui Kong

Zhi Chao Huang

Seong Ho Lee

Xin Meng

Mohammad Elbadry

Haitao Wang

Boyu Hu

Xiaochen Yang

Hamid Hatamkhani

Wayne Wah-Yuen Wong

Ramy Mohamed Yousry Ahmed Elsayed Awad

Kuo-J (Nick) Huang

A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k−1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.

Clock calibration for high-speed serial-link transmitters

In some implementations, the device may include a first circuit receiving an input signal having a first frequency, the first circuit including a first node and a second node. The device may include a second circuit receiving an input signal having a second frequency different from the first frequency, the second circuit including a first node and a second node, a first inductor coupled between the first node of the first circuit and the first node of the second circuit. The device may include a second inductor coupled between the second node of the first circuit and the second node of the second circuit, a first switch coupled between the first node of the second circuit and the second node of the second circuit, at least one differential inductor formed of the first inductor and the second inductor in response to the first switch being in a closed state.

Wide frequency range high speed clock multiplexer

A system may have a multiplexer and a controller. For a transition from a first pair of bits in first data provided to digital-to-analog converters (DACs) to a second pair of bits in second data, the controller may determine whether the transition is of a first type or of a second type, and in response to determining that the transition is of the first type, control the multiplexer to output the second pair of bits to the DACs. In response to determining that the transition is of the second type and the second pair of bits are to be swapped, the controller may control the multiplexer to output a swapped pair of bits to the DACs. Data output by the multiplexer based on the second data has a predetermined number of bits that have binary values different from those of corresponding bits in the first data.

System and method for transition aware binary switching for digital-to-analog converters (DACs)

An optical module includes an optical receiver with a complementary metal-oxide semiconductor (CMOS) transimpedance amplifier (TIA) and a digital signal processing (DSP) circuit. The DSP circuit is integrated with the CMOS TIA and facilitates adaptability of the CMOS TIA, and the CMOS TIA can adapt by using information provided by the DSP circuit.

Integrated transimpedance amplifier with a digital signal processor for high-speed optical receivers

In some implementations, a circuitry may include a series of symmetrical stages with an initial stage in the series coupled to an input signal having a first plurality of phases and an output stage in the series coupling an output signal comprising a second plurality of phases to a calibration engine, where a quantity of the phases in the output signal is increased based at least on a quantity of the symmetrical stages and a quantity of the first plurality of the phases in the input signal. In addition, the circuitry may include implementations, where the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include implementations, where the calibration engine outputs a current provided to the series, where the output current can be based at least on a calibrated frequency.

Method and system for injection locked divider with frequency calibration

Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier ('PGA') and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.

Integrated programmable gain amplifier (PGA) and protection circuit

A system is provided that includes a first electronic device, multiple second electronic devices coupled to the first electronic device via respective interfaces, and a clock generator coupled to the second electronic devices and configured to generate and provide a clock signal to each of the second electronic devices for clocking operation of the second electronic devices. The clock signal is a gapped clock signal having at least one gap created by the clock generator removing one or more clock pulses based on a synchronization signal, and the second electronic devices are configured to synchronize data transmission between the second electronic devices and the first electronic device via the interfaces using the at least one gap in the gapped clock signal to align the data transmission.

Synchronization of devices with a gapped reference clock

A solution for generating a clock using a quadrature delay can include a first plurality of in-phase (I) inverter pairs configured to output an I signal according to a first input and an inverted in-phase (inverted I) signal according to a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution can include a second plurality of quadrature (Q) inverter pairs configured to output a Q signal according to a third clock signal input and an inverted Q signal (inverted Q) according to a fourth clock signal input and a phase detector including a plurality of cells, each of which can receive at least one of the I signal, the inverted I signal, the Q signal or the inverted Q signal and include at least one or more transistors having a gate connected to a ground.

Systems and methods for quadrature delay clock generation

A system includes a dither generator module that includes a most significant bits (MSB) dither generator device that generates a first random value. The dither generator module also includes a least significant bits (LSB) dither generator device that generates a second random value. The system further includes a first digital to analog converter (DAC) that receives a sum of the first random value and the second random value and generates a dither signal based on the sum of the first random value and the second random value. The system also includes an analog to digital converter (ADC) that receives a sum of the dither signal and a sampled input signal and generates a first digitized signal. The system includes a subtraction module that subtracts the sum of the first random value and the second random value from the first digitized signal to produce a digitized output signal.

Split-dithering scheme in successive approximation analog to digital converter

A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.

Systems for and methods of phase interpolation

Systems and methods are related to a distributed amplification. An amplification device can include cells including a first cell and a second cell and transmission lines including a first line and a second line. The first cell is coupled to the first line, and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The device also includes a summer including a first input coupled to the first line and second input coupled to the second line. The summer is configured to provide an output signal.

Systems for and methods of wideband distributed amplification

An analog-to-digital converter (ADC) circuit includes a digital-to-analog converter (DAC) circuit, a comparator circuit, an encoder, and a compensation circuit. The DAC circuit receives a reference voltage and provides an output signal based on the reference voltage. The comparator circuit compares the output signal with an analog input signal and generates a comparison signal. A reset command is generated based on the output signal being greater than the analog input signal. The encoder splits a ripple associated with the reference voltage into multiple pulses in response to a reset command. The compensation circuit generates, responsive to the reset command, compensation pulses to compensate the multiple pulses.

Reference-ripple compensation technique for SAR ADC

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.

Successive approximation register analog to digital converter having adaptive current or voltage parameter adjustments

Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.

Systems for and methods of fractional frequency division

An apparatus, a system, and a communication device. The apparatus includes a substrate and a circuit formed on the substrate. The circuit includes a first transformer having first input nodes and first output nodes. The circuit further includes a second transformer having second input nodes and second output nodes. The first input nodes of the first transformer and the second input nodes of the second transformer are connected. At least one first output node of the first output nodes of the first transformer and at least one second output node of the second output nodes of the second transformer are connected. The circuit further includes a first capacitor connected to one of the first output nodes of the first transformer and to one of the second output nodes of the second transformer. The first capacitor is connected to a first ground.

System and apparatus for on-substrate circuit configured to operate as transformer

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Irvine, CA, United States of America

Jun Cao