Texas Instruments Corporation

Jun Cai

Binghua Hu

Akram Ali Salman

Krishna Praveen Mysore Rajagopal

The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.

LDMOS transistor and method of forming the LDMOS transistor with improved Rds*Cgd

An integrated circuit includes a Laterally Diffused MOSFET (LD-MOSFET) located over a semiconductor substrate. The LD-MOSFET transistor includes a dielectric filled trench at a surface of the semiconductor substrate, and a doped region of the semiconductor substrate adjacent the dielectric-filled trench. The doped region and the dielectric-filled trench share an interface that has a terminus at the surface of the semiconductor substrate. An oxide layer is located over the semiconductor substrate, including along a surface of the doped region and along a surface of the dielectric-filled trench. The oxide layer has a first thickness over the dielectric-filled trench and a second greater thickness over the doped region.

Transistors having gates with a lift-up region

A semiconductor device contains a Zener-triggered transistor having a Zener diode vertically integrated in a first current node of the Zener-triggered transistor. The first current node includes an n-type semiconductor material contacting a p-type semiconductor material in a substrate. The Zener diode includes an n-type cathode contacting the first current node, and a p-type anode contacting the n-type cathode and contacting the p-type semiconductor material. The semiconductor device may be formed using an implant mask, with an opening for the Zener diode. Boron and arsenic are implanted into the substrate in an area exposed by the opening in the implant mask. The substrate is subsequently heated to diffuse and activate the implanted boron and arsenic. The Zener-triggered transistor may be used in an ESD circuit or a snubber circuit.

Zener-triggered transistor with vertically integrated Zener diode

Disclosed examples include LDMOS transistors and integrated circuits with a gate, a body region implanted in the substrate to provide a channel region under a portion of the gate, a source adjacent the channel region, a drain laterally spaced from a first side of the gate, a drift region including a first highly doped drift region portion, a low doped gap drift region above the first highly doped drift region portion, and a second highly doped region portion above the gap drift region, and an isolation structure extending through the second highly doped region portion into the gap drift region portion, with a first end proximate the drain region and a second end under the gate dielectric layer, where the body region includes a tapered side laterally spaced from the second end of the isolation structure to define a trapezoidal JFET region.

Integrated circuit, LDMOS with bottom gate and ballast drift

Integrated circuit, LDMOS with trapezoid JFET, bottom gate and ballast drift and fabrication method

LDMOS transistor and method of forming the LDMOS transistor with improved RDS*CGD

In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.

Low substrate leakage Zener diode with modulated buried junction

In accordance with at least one embodiment of the invention, a transistor comprises a semiconductor, a first drift layer, a drain region, a body region, a source region, a shallow trench isolation region, a dielectric, and a gate. The first drift layer is formed in the semiconductor and has majority carriers of a first type. The drain region is formed in the first drift layer and has majority carriers of the first type. The body region is formed in the semiconductor and has majority carriers of a second type. The source region is formed in the body region and has majority carriers of the first type. The shallow trench isolation region is formed in the first drift layer and disposed between the drain region and the body region. The dielectric is formed on the semiconductor, and the gate is formed over the dielectric and has a lift-up region.

Low substrate leakage zener diode with modulated buried junction

LDMOS devices are disclosed. An LDMOS device includes at least one drift region disposed in a portion of a semiconductor substrate; at least one isolation structure at a surface of the semiconductor substrate; a D-well region positioned adjacent a portion of the at least one drift region, and an intersection of the drift region and the D-well region forming a junction between first and second conductivity types; a gate structure disposed over the semiconductor substrate; a source contact region disposed on the surface of the D-well region; a drain contact region disposed adjacent the isolation structure; and a double buffer region comprising a first buried layer lying beneath the D-well region and the drift region and doped to the second conductivity type and a second high voltage deep diffusion layer lying beneath the first buried layer and doped to the first conductivity type. Methods are disclosed.

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Allen, TX, United States of America

Jun Cai