Samsung Electronics Co., Ltd.

Samyang Biopharmaceuticals Corporation

Daewoo Electronics Co., Ltd.

Jun-Bae Kim

Seong-Jin Jang

Yang-Ki Kim

Young-Uk Chang

Sin-Ho Kim

Guw-Dong Yeo

Hyun-Ju Lee

Chul-Hwan Choo

Hye-Seung Yu

Tae-Sik Na

Chan-hee Jeon

Sun-Woo Kim

Young-Ok Cho

Seong-Woo Nam

Chang-hyun Bae

Jun-ho Shin

Hye-Sung Yoon

Jae-Hong Lee

An anti-adhesion composition with a good anti-adhesion property as well as a good biocompatibility, a surgical mesh composite with anti-adhesion property comprising the same and method for producing the same are provided.

Composition for anti-adhesion, surgical mesh composite with anti-adhesion property comprising the same and method for producing thereof

The present invention relates to a monofilament with a segmented pie structure formed by conjugated spinning of degradable polymers and non-degradable polymers, a hernia mesh having improved flexibility and biocompatibility, and a preparation method of the monofilament. More specifically, the hernia mesh of the present invention having improved flexibility and biocompatibility is prepared using the monofilament obtained by conjugated spinning of degradable polymers and non-degradable polymers into a segmented pie form, to control it to be gradually degraded in the body, whereby the stiffness of the early stage is removed, and thereby the foreign body sensation is also removed.

Process for preparing hernia mesh from monofilament

A self bias buffer circuit includes a buffer and bias controller. The buffer provides a self bias voltage based on a reference voltage and to be driven based on the self bias voltage. The buffer also generates an output signal based on a comparison of an input signal and the reference voltage. The bias controller adjusts the self bias voltage based on the reference voltage.

Self bias buffer circuit and memory device including the same

A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

Semiconductor memory device for controlling operation of delay-locked loop circuit

The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal.

Duty correcting circuit, delay-locked loop circuit and method of correcting duty

A calibration circuit includes a pad connected between an external resistor connected to a first voltage source and a first node, a first resistor unit connected between the first node and a second voltage source, a second resistor unit connected between a second node and the second voltage source, a first control unit for generating and outputting a first output signal, a first pull-down circuit connected between the second node and the first voltage source, a second pull-down circuit connected between a third node and the first voltage source, a second control unit for generating and outputting a second output signal, and a pull-up circuit connected between the third node and the second voltage source.

Calibration circuit

A semiconductor memory device includes a delay lock loop (DLL) performing a locking operation at a wide frequency range and reducing current consumption. The semiconductor memory device includes a (DLL) having serially connected delay cells that receive and delay an external clock signal, wherein a predetermined number of delay cells of the serially connected delay cells that are to perform a delay operation are turned on in response to a threshold frequency recognition signal and first and second delay cell on signals, and for generating an internal clock signal; and a controller for generating the threshold frequency recognition signal and the first and second delay cell on signals, which reduce current consumption of each of the serially connected delay cells and increase a period of delay time thereof, if more delay cells are to be turned on when a delay cell indicating a threshold frequency is turned on.

Semiconductor memory device having delay lock loop with wide frequency range and delay cell current reduction scheme

A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

A wideband delay-locked loop (DLL) circuit includes an internal clock signal generating unit providing an internal control signal by selecting and interpolating between two clock delay signals during a primary phase locking operation. The internal clock signal may be modified by a secondary phase locking operation if more delay is required to phase lock the internal clock signal to an external clock signal. A phase detection/control circuit generates various control signals based on a phase comparison of the internal clock signal and the external clock signal.

Wideband delay-locked loop (DLL) circuit

A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period.

On-die termination latency clock control circuit and method of controlling the on-die termination latency clock

Provided is a semiconductor device for performing a calibration operation without an external ZQ calibration command and a calibration method thereof. The semiconductor device includes a calibration circuit for performing a pull-down calibration operation in response to a pull-down calibration enable signal and a command control unit for generating the pull-down calibration enable signal in response to a DLL reset signal. The calibration method includes adjusting an impedance of a first pull-up resistance structure in response to pull-up calibration codes having a default value. A pull-down calibration enable signal may be generated in response to a DLL reset signal. A voltage of the first node and a reference voltage are compared by a comparator. The comparator outputs pull-down calibration codes based on the comparison. An impedance of a pull-down resistance structure is adjusted, so a resistance of the pull-down resistance structure is equal to a resistance of the first pull-up resistance structure.

Semiconductor devices having ZQ calibration circuits and calibration methods thereof

A semiconductor device and method of forming a pad thereof are provided. The device includes: a substrate; at least one first active region disposed in a first region of the substrate; at least one second active region disposed in a second region adjacent to the first region of the substrate; a plurality of first contacts disposed on the second active region; a first insulating layer disposed on the first active region and between the first contacts; a poly layer disposed on the first contacts and the first insulating layer; a plurality of second contacts disposed on the poly layer in the second region; a second insulating layer disposed between the second contacts and on the poly layer in the first region; and a pad disposed on the second insulating layer and the second contacts.

Semiconductor device and method of arranging pad thereof

A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the internal clock signal; a delay unit controller for generating a control signal and a selection signal in response to an output signal of the phase detector; a variable delay device (VDD), responsive to the control signal and a selection signal, to produce a delayed version of the external clock signal on a VDD output line, the variable delay device being configured such that, if the external clock signal undergoes a change from a first frequency to a second frequency significantly different than the first frequency, then a resultant load on the VDD output line nonetheless remains substantially the same.

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Seoul, South Korea

Jun-Bae Kim