Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Jumpei Sato

Takuya Futatsuyama

Kenichi Abe

Toshifumi Hashimoto

Yoshikazu Takeyama

Satoshi Yamano

Tsuyoshi Etou

Osamu Ooto

Souichi Minemura

A semiconductor memory device includes a memory array provided above a substrate in a first direction intersecting a surface of the substrate. A first peripheral circuit is provided between the substrate and the memory array. A second peripheral circuit is provided between the substrate and the memory array and apart from the first peripheral circuit in a second direction parallel to the surface of the substrate. A sense amplifier is provided between the substrate and the memory array and between the first and second peripheral circuits, and a word line switch circuit extending in the second direction is also provided. A length of the second peripheral circuit in the second direction is smaller than half of a length of the sense amplifier in the second direction.

Semiconductor memory device

In a semiconductor memory device, a first plane includes a first memory cell array provided above a substrate in a first direction. A first power supply circuit is provided between the substrate and the first memory cell array, and a first sense amplifier is provided between the substrate and the first memory cell array. A second plane includes a second memory cell array provided above the substrate and a second power supply circuit provided between the substrate and the second memory cell array. A second sense amplifier is provided between the substrate and the second memory cell array. When viewed in the first direction, the first power supply circuit and the first sense amplifier overlap the first memory cell array, and the second power supply circuit and the second sense amplifier overlap the second memory cell array.

According to one embodiment, a semiconductor memory device includes the following structure. A memory array is provided on a first-direction side of a substrate. The first direction intersects the substrate. The first peripheral circuit is provided between the substrate and the memory array. The second peripheral circuit is provided between the substrate and the memory array and on a second-direction side of the first peripheral circuit. The second direction intersects the first direction. The sense amplifier is provided between the substrate and the memory array and between the first and second peripheral circuits. A second-direction length of the second peripheral circuit is smaller than half a second-direction length of the sense amplifier.

A semiconductor memory device is provided that includes a plurality of memory blocks, arranged in a second direction, that are spaced from a semiconductor substrate in a first direction intersecting with a surface of the semiconductor substrate; a first wiring that is farther from the semiconductor substrate than the plurality of memory blocks in the first direction; a second wiring that is closer to the semiconductor substrate than the plurality of memory blocks in the first direction; a first contact; a first transistor with a first active region disposed in the semiconductor substrate, the second wiring being electrically connected to a first memory block among the plurality of memory blocks via the first transistor; and a second transistor where the second wiring being electrically connected to a second memory block among the plurality of memory blocks via the second transistor.

A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.

According to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first circuit including a plurality of transistors respectively connected to the plurality of bit lines and the sense amplifier; and a plurality of interconnects which are provided at a position higher than the bit lines in the first circuit and are not directly connected to the first circuit. The semiconductor storage device does not include, at a position higher than the plurality of interconnects, an interconnect which electrically connects two positions in the semiconductor storage device.

Semiconductor storage device

According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.

Semiconductor memory device, method for designing semiconductor memory device, and recording medium having designing method recorded therein

In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact.

Semiconductor device

According to one embodiment, a semiconductor device includes a semiconductor chip which includes a semiconductor integrated circuit provided in an insulator, a first pad a pad having an upper surface of which is exposed via an opening formed in the insulator, and capacitors provided in a capacitor region of the semiconductor chip under the pad. The capacitors are provided in the capacitor region to satisfy a rule of a coverage. And contacts respectively connected to two electrodes of the capacitors are provided at positions that do not vertically overlap the opening.

Semiconductor device including capacitor under pad

A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in a shape of a matrix along a plurality of parallel bit lines and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the bit lines; a sense amplifier which detects a voltage or a current of the bit line and decides the read data from each of the memory cells; a clamping transistor connected between the sense amplifier and the bit lines to determine a voltage in a charging mode of the bit lines by a clamp voltage applied to a gate thereof; and a clamp voltage generation circuit which generates the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the memory cells is longer.

A semiconductor integrated circuit includes a boost circuit configured to boost a power supply voltage so as to generate first and second voltages, the second voltage being lower than the first voltage, a load circuit supplied with the first voltage, and a capacitor. The capacitor has first and second diffusion regions, a first insulating film formed on a channel region, a first electrode formed on the first insulating film, a second insulating film formed on the first electrode, and a second electrode formed on the second insulating film. The second voltage is applied to the first electrode. The first voltage is applied to the second electrode. The power supply voltage is applied to at least one of the first and second diffusion regions.

Semiconductor integrated circuit

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the bit lines; a sense amplifier which detects a voltage or a current of the bit line, and which decides the read data from each of the memory cells; a clamping transistor which is connected between the sense amplifier and the bit lines, and which determines a voltage in a charging mode of the bit lines by a clamp voltage applied to a gate thereof; and a clamp voltage generation circuit which generates the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the memory cells is longer.

Growing community of inventors

Kawasaki, Japan

Jumpei Sato