Fujitsu Corporation

Jumpei Hongo

Masaki Deguchi

Ryuichi Kimura

Takayuki Moriyama

Ryohei Yaginiwa

Syuichi Musou

A packet processing device is implemented in a network that transmits priority packets and non-priority packets having a lower priority than the priority packets. The packet processing device includes: a packet storage, a gate, a controller, a detector, a generator, and a transmitter. The packet storage stores non-priority packets. The gate is provided on an output side of the packet storage. The controller controls the gate. The detector detects a transmission pattern of the priority packets. The generator generates, based on the transmission pattern of the priority packets, a gate control signal for controlling a gate of a packet processing device implemented in another node. The transmitter transmits the gate control signal to a destination of the priority packets.

Packet processing device and network system

A transmission apparatus executes a reception processing that receives a first alarm detected in a first transmission apparatus different from the own apparatus from among a plurality of transmission apparatus from a second transmission apparatus different from the own apparatus from among the plurality of transmission apparatus, executes a detection processing that detects a second alarm of the own apparatus, executes a mask processing that masks alarms including the first alarm received by the reception processing and the second alarm detected by the detection processing, and executes a sending processing that sends an alarm that is not masked by the mask processing from among the alarms to a third transmission apparatus different from the own apparatus and the second transmission apparatus from among the plurality of transmission apparatus or sending the alarm to a given apparatus different from any of the plurality of transmission apparatus.

Transmission apparatus, alarm transfer method and alarm transfer system

An apparatus includes a first counter circuit that counts a value of first statistical information divided in the time-direction from a first period; a second counter circuit that counts a value of second statistical information divided in the time-direction from a second period following the first period; a control circuit that divides by a specific time period unit and acquires the value of the first statistical information and the value of the second statistical information, and causes a first memory to store the value of the first statistical information, and causes a second memory to store the value of the second statistical information; and a switching circuit that switches the value of the statistical information acquired by the control circuit from the value of the first statistical information to the value of the second statistical information upon a start of the second period.

Growing community of inventors

Kawasaki, Japan

Jumpei Hongo