Hynix Semiconductor Inc.

Skhynix Inc.

Dongbu Electronics, Co. Ltd.

Dongbu Hitek Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Dongbu Anam Semiconductor, Inc.

Jum Soo Kim

Sung Mun Jung

Jung Ryul Ahn

Young Bok Lee

Young Ki Shin

Sang Bum Lee

Min Kuck Cho

Tae Gyun Kim

Min Kyu Lee

Sang Hyun Oh

Hee Hyun Chang

Ji Hyung Yune

A semiconductor memory device, a memory system having the same, and a method of operating the same are provided. The semiconductor memory device includes a plurality of memory cells electrically coupled between a source select transistor and a drain select transistor, a peripheral circuit configured to perform a program operation on the plurality of memory cells, and a control logic unit configured to control the operation of the peripheral circuit so that at least two memory cells of the plurality of memory cells adjacent to the source select transistor and at least two memory cells of the plurality of memory cells adjacent to the drain select transistor are programmed to have a relatively fewer number of data bits than that of remaining memory cells of the plurality of memory cells in the program operation.

Semiconductor memory device, memory system having the same, and method of operating the same

A semiconductor device includes a first memory string and a second memory string. The first memory string includes a plurality of first main memory cells formed on a pipe transistor of a semiconductor substrate and a plurality of first dummy memory cells connected between the first main memory cells and a common source line. The second memory string includes a plurality of second main memory cells formed on the pipe transistor and a plurality of second dummy memory cells connected between the second main memory cells and a bit line. The number of the second dummy memory cells is greater than the number of the first dummy memory cells.

Semiconductor device

The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.

Semiconductor device and method of manufacturing the same

A method of operating a semiconductor memory device includes a memory array having memory cell strings including a first and a second memory cell groups having memory cells, a first and a second dummy elements, a drain select transistor and a source select transistor, wherein the first memory cell group and the second memory cell group are arranged between the drain select transistor and the source select transistor; connecting electrically the first memory cell group to the second memory cell group during a program operation or a read operation of the first memory cell group or the second memory cell group; and performing separately an erase operation of the first memory cell group and an erase operation of the second memory cell group, selecting simultaneously one of the first dummy element and the second dummy element during the erase operation of the selected memory cell group.

Semiconductor memory device and method of operating the same

A method of operating a flash memory device wherein the width of threshold voltage distribution of memory cells is adjusted by setting different conditions of a program operation in accordance with levels of threshold voltages of the memory cells. As a result, width of the threshold voltage distribution of memory cells may be narrowed.

Method of operating a flash memory device

A method of manufacturing a NAND flash memory device, including the steps of forming gates over a semiconductor substrate; forming a junction region over the semiconductor substrate between the gates; forming a buffer oxide film on the gates and the semiconductor substrate; stripping the buffer oxide film at one side of the gates; forming a nitride film spacers over the sidewalls of the gates; forming a self-aligned contact process (SAC) nitride film and an insulating film over the entire structure; etching regions of the insulating film and the SAC nitride film to form a contact through which the junction region is exposed; and forming a conductive film to bury the contact, thereby forming a contact plug.

Method of manufacturing NAND flash memory device

The present invention relates to a method manufacturing a code address memory (CAM) cell. The present invention uses a dielectric film in which an oxide film and a nitride film between a floating gate and a control gate in a flash memory cell are stacked as a gate insulating film between a semiconductor substrate and a gate in the CAM cell. Therefore, the present invention can reduce the area of a peripheral circuit region and stably secure repaired data since the CAM cell can be stably driven at a low operating voltage and additional boosting circuit is thus not required.

Method for manufacturing code address memory cell by which a stack insulating film of an oxide film and a nitride film used as a dielectric film in a flash memory is used as a gate oxide film

A non-volatile memory device and a method of manufacturing the same, in which the program speed can be enhanced and the interference phenomenon can be reduced. The non-volatile memory device includes a semiconductor substrate having an active region defined by isolation layers arranged in one direction, a control gate arranged vertically to the direction in which the isolation layers are arranged, a floating gate formed on the active region below the control gate and having a lateral curve so that the floating gate has a width narrowed upwardly, a gate insulating layer formed between the floating gate and the semiconductor substrate, and a dielectric layer formed between the floating gate and the control gate.

Method of fabricating a non-volatile memory device

The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.

Non-volatile memory device and fabricating method thereof

The present invention provides a non-volatile memory device and fabricating method thereof, in which a height of a floating gate conductor layer pattern is sustained without lowering a degree of integration and by which a coupling ratio is raised. The present invention includes a trench type device isolation layer defining an active area within a semiconductor substrate, a recess in an upper part of the device isolation layer to have a prescribed depth, a tunnel oxide layer on the active area of the semiconductor substrate, a floating gate conductor layer pattern on the tunnel oxide layer, a conductive floating spacer layer provided to a sidewall of the floating gate conductor layer pattern and a sidewall of the recess, a gate-to-gate insulating layer on the floating fate conductor layer pattern and the conductive floating spacer layer, and a control gate conductor layer on the gate-to-gate insulating layer.

The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer. The present invention includes forming a mask layer pattern on a semiconductor substrate to expose a device isolation area but to cover an active area thereof, the mask layer pattern comprising a first insulating layer pattern and a second insulating layer pattern stacked thereon, forming a trench in the semiconductor substrate corresponding to the device isolation area, removing an exposed portion of the first insulating layer pattern enough to expose a portion of the semiconductor substrate in the active area adjacent to the trench, forming a sidewall oxide layer on an inside of the trench and the exposed portion of the semiconductor substrate, filling up the trench with a third insulating layer to cover the sidewall oxide layer, and removing the mask layer pattern.

Trench isolation method in flash memory device

An active region and a trench region are formed on a semiconductor substrate. The trench region is filled with a dielectric material to form an isolation layer. Oxide and polysilicon layers are formed on the semiconductor substrate. A second polysilicon layer, a second oxide layer, and a first polysilicon layer are patterned to form a plurality of gate lines. Deep ion implantation in a deep portion of the active region is performed using a self-aligned source mask. The active region and the trench region are exposed through the self-aligned source mask by etching the isolation layer between the plurality of gate lines using the self-aligned source mask to form a common source region. Ions are implanted in the common source region using the self-aligned source mask.

Flash memory cell and method for manufacturing the same

The present invention provides a method of fabricating a flash memory device, in which floating gates in neighbor cells are separated from each other without using photolithography, which enhances electrical characteristics of the device, and which facilitates a cell size reduction. The present invention includes forming a mask defining a trench forming area on a semiconductor substrate, forming a trench in the semiconductor layer by removing a portion of the semiconductor layer using the mask, forming a device isolation layer filling up the trench to maintain an effective isolation layer thickness exceeding a predefined thickness, removing the mask, forming a conductor layer over the substrate including the device isolation layer, planarizing the conductor layer and the device isolation layer to lie in a same plane, and forming an insulating layer over the substrate including the conductor patterns.

Growing community of inventors

Kyungki-do, South Korea

Jum Soo Kim