Intel Corporation

Julius Yuli Mandelblat

Shlomo Raikin

Larisa Novakovsky

Michael Mishaeli

Geeyarpuram N Santhanakrishnan

Mohan J Kumar

Ravishankar Iyer

Andrew J Herdrich

Ganapati Srinivasa

Ehud Cohen

Theodros Yigzaw

Edwin Verplanke

Jose Andy Vargas

Jeffrey D Chamberlain

Hisham Shafi

Zeev Sperber

Bret L Toll

Efraim Rotem

Eliezer Weissmann

Ronak Singhal

Tsvika Kurts

Zvika Greenfield

Asaf Rubinstein

Christopher C Gianos

Alexander Gendler

Ahmad Yasin

Daniel Greenspan

Rajshree Chabukswar

Joydeep Ray

Vincent J Zimmer

Robert Valentine

Rajesh M Sankaran

Tsung-Yuan Charles Tai

Raanan Sade

Blaise B Fanning

Yen-Cheng Liu

Ron Gabor

Eugene Gorbatov

Aravindh V Anantaraman

Russell Jerome Fenger

Lihu Rappoport

Kai Cheng

Stephen R Van Doren

Stephen T Palermo

Rupin H Vakharwala

Zeev Offen

Anant V Nori

Michael W Chynoweth

Rajaram Regupathy

Nadav Bonen

Alexander Lyakhov

Avi Mendelson

Vadim Bassin

Abraham Mendelson

Israel Diamand

Oded Lempel

Jeffrey D Gilbert

Ariel Berkovits

Subrata Banik

Chen Koren

Moty Mehalel

George Leifman

Eric R Wehage

Eran Shifer

Monica Gupta

Lev Makovsky

Ariel Sabba

Ron Shalev

Leon Polishuk

Niv Tokman

Nir Misgav

Pavel Konev

Nir Sucher

Evgeny Bolotin

Daniel Skaba

Michael Israeli

Itai Samoelov

Michelle J Moravan

Omer Barak

Dannie G Feekes

Techniques and mechanisms for providing a thread scheduling hint to an operating system of a processor which comprises first cores and second cores. In an embodiment, the first cores are of a first type which corresponds to a first range of sizes, and the second cores are of a second type which corresponds to a second range of sizes smaller than the first range of sizes. A power control unit (PCU) of the processor is to detect that an inefficiency, of a first operational mode of the processor, would exist while an indication of an amount of power, to be available to the processor, is below a threshold. Based on the detecting, the PCU hints to an executing software process that a given core is to be included in, or omitted from, a pool of cores available for thread scheduling.

Device, method and system to provide thread scheduling hints to a software process

Methods, apparatus, systems, and articles of manufacture to increase boot performance are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: during a boot process: identify a boot task that is to be performed during the boot process; execute the boot task using a first processor component; collect data corresponding to the execution of the boot task on the first processor component; categorize the boot task based on the collected data; and generate an entry for a boot table based on the categorization, the boot table used to schedule the boot task on at least one of the first processor component or a second processor component different than the first processor component based on the categorization.

Methods and apparatus to increase boot performance by categorizing boot tasks

Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.

Systems, apparatuses, and methods for resource bandwidth enforcement

An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Apparatus and method for detecting and recovering from data fetch errors

Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.

Performance monitoring in heterogeneous systems

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

Apparatus and method for adaptively scheduling work on heterogeneous processing resources

Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms

An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.

Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structures

One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.

Architecture for dynamic transformation of memory configuration

Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

Systems and methods for enhancing BIOS performance by alleviating code-size limitations

Integrated circuits, systems and methods are disclosed in which data bits protected by error correction code (ECC) detection and correction may be increased such that a combination of primary and additional bits may also be ECC protected using existing ECC allocation, without affecting ECC capabilities. For example, the additional bits may be encoded into phantom bits that are in turn used in combination with the primary bits, to generate an ECC. This ECC may then be combined with the primary bits to form a code word. The code word may be transmitted (or stored) so that when the data bits are received (or retrieved), assumed values of the phantom bits may be decoded, using the ECC, back into the additional bits without the phantom bits or the additional bits ever having transmitted (or stored).

Use of error correcting code to carry additional data bits

Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

Cache allocation with code and data prioritization

An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

Apparatus and method for memory-hierarchy aware producer-consumer instruction

Growing community of inventors

Haifa, Israel

Julius Yuli Mandelblat