Nvidia Corporation

Julius Vanderspek

Nicholas P Wilt

Ian Buck

Jayant B Kolhe

Bastiaan Aarts

One embodiment sets forth a method for efficiently determining memory resource dependencies between instructions included in a software application. For each instruction, a dependency analyzer uses overlapping search techniques to identify one or more overlaps between the memory elements included in the current instruction and the memory elements included in previous instructions. The dependency analyzer then maps objects included in the instructions to a set of partition elements wherein each partition element represents a set of memory elements that are functionally equivalent for dependency analysis. Subsequently, the dependency analyzer uses the set of partition elements to determine memory dependencies between the instructions at the memory element level. Advantageously, the disclosed techniques enable the compiler to retain an acceptable compilation speed while tuning the instruction ordering at a fine-grained memory element level, thereby increasing the speed at which the processor may execute the software application.

Techniques for determining instruction dependencies

One embodiment of the present invention sets forth a technique for performing fast integer division using commonly available arithmetic operations. The technique may be implemented in a four-stage process using a single-precision floating point reciprocal in conjunction with integer addition and multiplication. Furthermore, the technique may be fully pipelined on many conventional processors for overall performance that is comparable to the best available high-performance alternatives.

Integer division using floating-point reciprocal

One or more embodiments of the invention set forth techniques to perform integer division using a floating point hardware unit supporting floating point variables of a certain bit size. The numerator and denominator are integers having a bit size that is greater than the bit size of the floating point variables supported by the floating point hardware unit. Error correcting techniques are utilized to account for any loss of precision caused by the floating point operations.

High precision integer division using low precision hardware operations and rounding techniques

One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.

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San Jose, CA, United States of America

Julius Vanderspek