Loral Aerospace Corp.

Ford Motor Company Limited

Ford Aerospace & Communications Corporation

Julius Lange

Gary L Wagner

Elbert L Turner

Timothy Halloran

A transversal filter allrate equalizer for use at intermediate frequency. The equalizer includes a signal divider coupled to receive the intermediate frequency input signal and a transversal filter comprising a plurality of analog delay lines and a plurality of multiplying circuits. The plurality of analog delay lines are coupled to the signal divider for producing a time-shifted replica of an intermediate frequency input signal. The plurality of multiplying circuits are respectively coupled to the delay lines for weighting the time-shifted replicas of the input signal by complex numbers, W.sub.i. A signal combiner is coupled to the plurality of multiplying circuits for recombining the time-shifted and weighted replicas of the input signal to produce an equalized output signal. The delay lines operate at an intermediate frequency, and produce a time delay for the modulation and a phase shift for the carrier. The phase shift may be compensated for by adjusting the phases of the tap weights, W.sub.i. The equalizer reduces distortion and intersymbol interference in high data rate digital communications systems, such as modems, and the like.

Transversal filter allrate equalizer for use at intermediate frequency

An improved wideband double balanced GaAs mixer is presented and includes a plurality of FETs which are operative to couple a plurality of input signals to a diode ring quad wherein the signals are mixed, producing output IF signals composing multiples of the sum and difference frequency of the alternating input signals. In a first embodiment, a first pair of FETs is coupled to an input RF signal, and a second pair of FETs is coupled to an input LO signal. The first pair of FETs is driven in phase by the RF signal, while the second pair of FETs is driven in push-pull by the LO signal. This second pair of FETs is operative to alternately switch opposite sides of the diode ring quad into a conductive state wherein the mixing of the RF and LO signals take place.

CRT update wideband double balanced mixer

This on-line circuit estimates the bit error rate (BER) of a binary data signal stream in the presence of noise uncorrelated with the signal. For a binary data signal having two states, e.g., plus V and minus V biased around a specified reference level (REF), the circuit counts the number of instances in which the received signal deviates more than 2V from the reference level. This accumulated count gives an accurate estimate of the BER over several orders of magnitude variation of the BER. One embodiment counts just the deviations in a positive direction. This circuit functions independently of any bit pattern and can be used for on-line monitoring without decreasing the information carrying capability of the link. The time required to accumulate a statistically significant sample is the same as for a direct comparison between sent and received bits.

On-line bit error rate estimator

An adaptive equalizer for improving the quality of digital data contained in an electrical input signal supplied to the equalizer. The equalizer compensates for amplitude and delay distortion affecting the quality of the digital data contained in the electrical input signal. The equalizer includes a delay line having a plurality of discrete time delay elements and in a plurality of taps coupled to the delay elements. A clock circuit provides a plurality of clock signals of identical frequency but different phase, thereby, dividing a pre-selected time interval into a plurality of time-slots. A sequential switch controlled by the clock signals sequentially connects the delay line taps to a quality detector which also has as an input the equalizer output signal. The quality detector generates a signal, during each of the time slots, that represents the quality of the equalizer output signal. The criteria for the equalizer output signal quality is its squareness, and the quality detector output signals are used to control counters which may be incremented or decremented, as required, to improve the equalizer output signal quality. The digital outputs from the counters are supplied to digital-to-analog converters and the resulting analog signals are applied to voltage controlled amplifiers. The signals from the delay line taps are applied to the voltage controlled amplifiers in the equalizer and thereafter are summed to produce the equalizer output signal. The adjustment of the counters either up or down changes the gain of the voltage controlled amplifiers to improve the squareness of the equalizer output signal in a closed-loop manner. The preferred form of the equalizer of the invention is used to improve the quality of two channels of digital data obtained from the demodulation of a transmitted signal that is quadrature-phase-shift keyed. Thus, the two channels of data have identical data bit rates.

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Sunnyvale, CA, United States of America

Julius Lange