Intel Corporation

Julio Gago

Roger Gramunt

Roger Espasa

Jose Gonzalez

Rolf Kassa

Santiago Galan

Edward Thomas Grochowski

Yen-Kuang Chen

Victor W Lee

Jatin Chhugani

Mikhail Smelyanskiy

Ganesh Suryanarayan Dasika

Changkyu Kim

Victor Moya Del Barrio

Benjamin C Chaffin

Jason W Brandt

Andrew F Glew

Avinash Sodani

Jonathan D Combs

Aditya Kesiraju

Ramon Matas

Alexey Suprun

Ed Grochowski

Chung-Lun Chan

Rammohan Padmanabhan

Neal S Moyer

Vikram S Sundaram

Gerardo A Fernandez

Michael S Yang

A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

Method, system, and apparatus for page sizing extension

In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.

Scalable event handling in multi-threaded processor cores

In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.

Sharing TLB mappings between contexts

Some implementations disclosed herein provide techniques and arrangements for indicating a length of an instruction from an instruction set that has variable length instructions. A plurality of bytes that include an instruction may be read from an instruction cache based on a logical instruction pointer. A determination is made whether a first byte of the plurality of bytes identifies a length of the instruction. In response to detecting that the first byte of the plurality of bytes identifies the length of the instruction, the instruction is read from the plurality of bytes based on the length of the instruction.

Indicating a length of an instruction of a variable length instruction set

A region or group of pixels may be textured as a unit, using a range specifier and one or more anchor pixels to define the group. In some embodiments, processing grouped pixels improves efficiency.

Grouping pixels to be textured

A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.

Texture unit for general purpose computing

A texture unit may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.

Growing community of inventors

Barcelona, Spain

Julio Gago