Motorola Corporation

Semiconductor Components Industries, LLC

Freescale Semiconductor,inc.

Julio C Costa

Ernest Schirmann

Marino J Martinez

Olin L Hartin

Gary Horst Loechelt

Peter J Zdebel

Adolfo C Reyes

Misbahul Azam

Elizabeth C Glass

Mariam G Sadaka

Nyles Wynn Cody

Charles E Weitzel

Jenn-Hwa Huang

Paul W Sanders

James P Morgan

David K Lovelace

Bor-Yuan C Hwang

Wayne R Burger

Colby Greg Rampley

Daniel J Lamey

John L Freeman, Jr

Christopher Paul Dragon

David Q Ngo

Alan D Wood

Natalino Camilleri

Mark R Wilson

Wendy L Valentine

Irfan Rahim

Troy E Mackie

A method for fabricating an RF enhancement mode FET () having improved gate properties is provided. The method comprises the steps of providing () a substrate () having a stack of semiconductor layers () formed thereon, the stack including a cap layer () and a central layer () defining a device channel, forming () a photoresist pattern () over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating () an implant region () in the unmasked region, and (b) removing () the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.

Advanced RF enhancement-mode FETs with improved gate properties

An integrated circuit ( ) includes high performance complementary bipolar NPN and PNP vertical transistors ( ). The NPN transistor is formed on a semiconductor substrate whose surface ( ) is doped to form a PNP base region ( ). A film ( ) is formed on the surface with an opening ( ) over an edge of the base region. A first conductive spacer ( ) is formed along a first sidewall ( ) of the opening to define a PNP emitter region ( ) within the base region. A second conductive spacer ( ) is formed along a second sidewall ( ) of the opening to define a PNP collector region ( ).

Integrated circuit with a high speed narrow base width vertical PNP transistor

A semiconductor component ( ) includes a semiconductor substrate ( ) that is formed with trench ( ). A semiconductor layer ( ) is formed in the trench for coupling a control signal (V ) through a sidewall ( ) of the trench to route a current (I ) through a bottom surface ( ) of the trench.

Heterojunction semiconductor device and method of manufacturing

A method of manufacturing a semiconductor component includes forming an electrically insulative layer ( ) over a semiconductor substrate where a first portion of the electrically insulative layer is located over a first region ( ) of the semiconductor substrate and where a second portion of the first layer is located over a second region ( ) of the semiconductor substrate. An isolation region ( ) is formed in the semiconductor substrate between the first and second regions of the semiconductor substrate. After forming the isolation region, the second portion of the first layer is removed, and, after removing the second potion of the first layer, an epitaxial layer ( ) is grown over the second region of the semiconductor substrate.

Method of manufacturing a semiconductor component

An enhancement mode RF device and method of fabrication includes a stack of compound semiconductor layers, including a central layer defining a device channel, a doped cap layer, and a buffer epitaxially grown on a substrate. Source and drain implant areas, extending at least into the buffer, are formed to define an implant free area in the device channel between the source and drain. Source and drain metal contacts are positioned on an upper surface of the central layer. Several layers of insulation and dielectric are positioned over the device and a gate opening is formed and filled with gate metal. During epitaxial growth, the doped cap layer is tailored with a thickness and a doping to optimize channel performance including gate-drain breakdown voltage and channel resistance.

Enhancement mode RF device and fabrication method

An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.

Semiconductor device using a barrier layer between the gate electrode and substrate and method therefor

A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Single supply HFET with temperature compensation

A semiconductor device includes a transistor (30, 51) having a gate electrode (15, 52) wherein the gate electrode (15, 52) has a highly resistive portion (24, 25, 55). The highly resistive portion (24, 25, 55) is integrated into the gate electrode (15, 52) and is coupled to the gate electrode (15, 52) using a via-less contact method.

Semiconductor transistor with stabilizing gate electrode

A semiconductor device (20) is formed on a compound semiconductor substrate (21). The semiconductor device (20) is oriented on the surface (40) of the compound semiconductor substrate (21) such that the physical forces that result from the thermal heating or cooling of the compound semiconductor substrate (21) are essentially equal. This orientation reduces the variability of the drain to source current of the semiconductor device (20) as the semiconductor device (20) is operated at different temperatures.

Compound semiconductor device having reduced temperature variability

A semiconductor device (10) is formed in a semiconductor substrate (11) that acts as a collector region. A base region (12) is formed in the semiconductor substrate (11) and an emitter region (52) is formed such that it contacts at least a portion of the base region (12). A conductive layer (28) is used to provide electrical connection to the emitter region (52). The portion of the conductive layer (28) above the emitter region (52) is counter-doped to address the problems of an interfacial oxide layer (27) that exists between the emitter region (52) and the conductive layer (28).

Semiconductor device and method of making

A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.

Monolithic high frequency integrated circuit structure having a grounded

A varactor (10, 115, 122) is formed using a BICMOS process flow. An N well (28) of a varactor region (13) is formed in an epitaxial layer (22) by doping the epitaxial layer (22) with an N type dopant. A cathode region (55, 132) is formed in the N well (28) by further doping the N well (28) with the N type dopant. Cathode electrodes (91, 114) are formed by patterning a layer of polysilicon (62, 86) over the epitaxial layer (22). Subsequently, the cathode electrodes (91, 114) are doped with an N type dopant. A region adjacent the cathode region (55, 132) is doped to form a lightly doped region (103, 117). The lightly doped region (103, 117) is doped with a P type dopant to form an anode region (109, 119).

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Phoenix, AZ, United States of America

Julio C Costa