International Business Machines Corporation

Julio Alejandro Maldonado

Michael Anthony Christo

David Michael Green

Diana D Zurovetz

Roger Donell Weekly

Tingdong Zhou

Rodolfo Lopez

Louie Arthur Dickens

Pedro V Torres

Samuel Wynne Yang

Juan G Rivera

Alberto Garza

Emile L Kowalski

Alexander David Hames

Jose L Rodriquez

Tingdong Zhang

Diana M Zurovetz

A method for cognitive-based traffic incident snapshot triggering comprises acquiring data, via a first agent, from each of a plurality of local sensors. The first agent is configured to acquire the data from each of the plurality of local sensors in windows having a first window size. The method also comprises acquiring data, via a second agent, from each of a subset of the plurality of local sensors in windows having a second window size; detecting a pattern in the data acquired via the second agent, the pattern indicating a traffic incident; and in response to detecting a pattern indicating the traffic incident, aggregating all data acquired via the first agent from a time when the pattern was detected until motion of the vehicle stops with the pre-determined number of windows of data stored at the time when the pattern was detected.

Cognitive-based traffic incident snapshot triggering

For printed circuit board ('PCB') design, methods, systems, and apparatuses are disclosed. One apparatus includes a component ID module that identifies a PCB component to be placed on a current board design; a search module that displays one or more instances of previous board designs containing the identified PCB component, wherein displaying the one or more instances of previous board designs containing the identified PCB component comprises displaying a region surrounding the identified PCB component; and an import module that imports a selected portion of a board design into the current board design from a selected one of the instances of previous board designs containing the identified PCB component.

Printed circuit board design

Methods to perform an operation comprising receiving an indication of a type and a target of a fault to inject in a network, the network comprising a plurality of devices and a plurality of network elements, generating at least a first predicted network map depicting a predicted configuration of the plurality of devices and network elements subsequent to injecting the fault in the network, injecting the fault at the target in the network, generating an actual network map depicting an actual configuration of the plurality of devices and network elements, identifying, based on a comparison of the first predicted network map and the actual network map, at least one difference in the predicted and actual configurations, and outputting for display an indication of the identified at least one difference.

Testing and delivering verification of network configurations

Systems and computer program products to perform an operation comprising receiving an indication of a type and a target of a fault to inject in a network, the network comprising a plurality of devices and a plurality of network elements, generating at least a first predicted network map depicting a predicted configuration of the plurality of devices and network elements subsequent to injecting the fault in the network, injecting the fault at the target in the network, generating an actual network map depicting an actual configuration of the plurality of devices and network elements, identifying, based on a comparison of the first predicted network map and the actual network map, at least one difference in the predicted and actual configurations, and outputting for display an indication of the identified at least one difference.

Power may be supplied to an electronic module according to various techniques. In one general implementation, for example, a system for supplying power to an electronic module may include a printed circuit board, the electronic module, and a conductive foil. The board may include a number of contact locations on a first side, with at least one of the contact locations electrically coupled to a via to a second side of the board. The electronic module may be electrically coupled to the contact locations on the first side of the board and receive electrical power through the at least one contact location electrically coupled to a via. The foil may be adapted to convey electrical power for the electronic module and electrically coupled on the second side of circuit board to at least the via electrically coupled to a contact location that receives electrical power for the electronic module.

Electronic module power supply

A child component ID module identifies child components connected to a parent component in response to selection of the parent component for placement on a PCB. The child components identified from component connections of a logic design. A child placement module places the child components around the parent component after placement of the parent component, where each child component is placed in compliance with constraints of the child components. A constraint highlight module identifies, on a PCB layout, an allowable area for component placement and prohibited areas for non-placement after selection of the component. The component is a parent component or a child component identified from component connections of a logic design of an electronic circuit design. The apparatus includes a constraint de-highlight module that removes identification on the PCB layout of the allowable area and the one or more prohibited areas in response to placement of the component.

Smart placement, visualization and optimization methodology for component placement and planning

Identifying and resolving issues with placement of plated through vias in voltage divider regions of a printed circuit board ('PCB') layout. Search parameters indicate an area of the PCB layout to be analyzed, and vias meeting the search parameters are evaluated for placement issues. Upon detecting a placement issue for a via, a solution is determined that addresses and resolves the placement issue of the via. The resolution in an embodiment includes modifying an adjacent power shape, modifying a region between shapes, and/or modifying via placement to minimize risks that include potential shorting, partially-connected vias, and/or poor plated barrel adhesion.

Identifying and resolving issues with plated through vias in voltage divider regions

The present disclosure provides a method, computer program product, and system of document implementation tool for pcb refinement. In some embodiments, the system includes a current data object with at least a PCB design, a PCB data store, a feature identifier configured to identify one or more features in at least the current PCB design, a comparison engine, configured to compare features in the current PCB design and known features in the PCB data store, a classification engine configured to classify one or more discrepancies between the current PCB design and the PCB data store based on a size of each of the one or more discrepancies, a determination engine configured to determine changes needed to resolve the one or more discrepancies, and a reporting engine configured to report the one or more discrepancies to a user.

Document implementation tool for PCB refinement

The present disclosure provides a method, computer program product, and system of document implementation tool for pcb refinement. In some embodiments, the system includes a current data object with at least a current PCB design, a printed circuit board (PCB) data store, where the plurality of data objects has known features, a feature identifier configured to identify one or more features in at least the current PCB design, a comparison engine, configured to compare features in the current PCB design and known features in the PCB data store that have been linked to one or more manufacturing defects, a classification engine configured to classify one or more feature between the current PCB design and the PCB data store, a determination engine configured to determine one or more changes in the current PCB design likely to decrease an occurrence of a manufacturing defect.

An approach is provided in which an information handling system creates a printed circuit board (PCB) layout based upon a set of packaged components. The information handling system modifies the PCB layout based upon an adjustment of the set of packaged components and generates board design data based on the modified PCB layout. In turn, the information handling system simulates the PCB layout using the board design data.

Dynamic power integrity and simulation for PCB design

An apparatus for detecting printed circuit board ('PCB') design violations includes an analysis module that analyzes a position of a trace on a PCB design to determine conductivity of a design material over which the trace is being added and/or an electrical property of the trace at the position. The apparatus further includes an identification module that identifies, in real time, a void violation on the PCB design in response to the design material including a non-conductive material and/or a reference voltage violation on the PCB design in response to the position including a voltage and a notification module that notifies a user of the void violation and/or the reference voltage violation. At least a portion of said modules include hardware circuits, a programmable hardware device, and/or executable code stored on one or more non-transitory computer-readable storage media.

Detecting printed circuit board design violations

Via array placement on a printed circuit board (PCB) outline including receiving, by a PCB design module, via array data from a user; generating, by the PCB design module, a via array based on the via array data from the user, including placing the via array on the PCB outline, wherein the via array comprises a grid of vias; detecting, by the PCB design module, that a first PCB element has been placed on top of a first portion of the via array on the PCB outline; removing, by the PCB design module, the first portion of the via array under the first PCB element, wherein a second portion of the via array remains on the PCB outline after removing the first portion of the via array; and generating, by the PCB design module, a PCB design document using the PCB outline and the second portion of the via array.

Via array placement on a printed circuit board outline

Dynamic electronic printed circuit board (PCB) design is provided. A test net on a PCB is dynamically created utilizing a first rule defining a net parameter and a second rule defining a padstack geometric parameter. A first evaluation of one or more nets having a first padstack is performed against the first rule. A second evaluation of both the first padstack and a reference padstack determined to be adjacently positioned to the first padstack is performed against the second rule. Based on the evaluations, a potential test net having a potential test padstack is dynamically selected from the evaluated nets. The selected potential test net is dynamically transformed into the test net. The dynamic transformation includes modifying the potential test padstack and/or the reference padstack utilizing the second rule. The dynamic creation of the test net improves the efficiency of electronic PCB design by mitigating time and footprint consumption.

Growing community of inventors

Austin, TX, United States of America

Julio Alejandro Maldonado