Vsora

Dibcom

Parrot Faurecia Automotive

Julien Schmitt

Khaled Maalej

Pierre-Emmanuel Bernard

Trung Dung Nguyen

Amaury Demol

Emmanuel Hamman

Yannick Levy

Trung-Dung Nguyen

A processor comprising a control unit and a plurality of processing units interacting according to an operating architecture imposed dynamically by the control unit from among at least two of the following architectures: a single instruction multiple data (SIMD) stream architecture, a multiple instruction single data (MISD) stream architecture, and a multiple instruction multiple data (MIMD) stream architecture. The operating architecture is imposed dynamically by the control unit according to: configuration functions included in a machine code, and/or data to be processed and current processing instructions received as input of the processor.

Dynamic processor architecture control

A computing device comprising: a plurality of ALUs; a set of registers; a memory; a memory interface between the registers and the memory; a control unit controlling the ALUs by generating: at least one cycle i including both implementing at least one first computing operation by way of an arithmetic logic unit and downloading a first dataset from the memory to at least one register; at least one cycle ii, following the at least one cycle i, including implementing a second computing operation by way of an arithmetic logic unit, for which second computing operation at least part of the first dataset forms at least one operand.

SMID processing unit performing concurrent load/store and ALU operations

A method for data processing implemented by computer means and comprises: for a plurality of objects of the data processing, conducting an analysis of a computer code of the data processing defining a use of said objects in the data processing, on the basis of the analysis of the computer code (COD), allocating each object to one of a plurality of memory areas for the construction and then the destruction of each object in the corresponding memory area during the data processing, in such a way that, during the data processing, each memory area exhibits stack operation.

Method for data processing

This device () includes elements () for receiving an analogical signal including a data signal in a frequency channel, elements () for amplifying the received signal, elements () for filtering the amplified signal so as to cut out frequencies outside the frequency channel of the data signal, members () for converting the filtered analogical signal into a digital signal, elements () for measuring the power (P) of the whole received signal after amplification and before filtering, and members () for determining an amplification control signal for the received signal amplification as a function of the received signal measured power (P).

Method and device for digitizing an analogical signal

A wireless signal amplification system including amplification apparatus () consisting of numerous different amplifiers (to) which are distributed in an analogue processing chain (). Also, a converter () for converting analogue signals into digital signals which, at input, are connected to the outlet of the analogue processing chain () and, at output, are connected to at least the gain control circuit () of the amplification apparatus () according to a value that is representative of a characteristic of the wireless signal (). In this way, sampling of the wireless signal () by the converter () is optimized. The gain control circuit () establishes an average gain control signal (), and also has, for each of the amplifiers (to), a device for calculating an individual gain control signal (to) according to a transfer function (Hto H) which is specific to each amplifier and which is applied to the average gain control signal.

Growing community of inventors

Palaiseau, France

Julien Schmitt