Imec Vzw

Imec

Vrije Universiteit Brussel

Globalfoundries Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Globalfoundries U.S. Inc.

Stichting Imec Nederland

Julien Ryckaert

Juergen Boemmels

Naoto Horiguchi

Trong Huynh Bao

Pieter Weckx

Eugenio Dentoni Litta

Boon Teik Chan

Guillaume Bouche

Francky Catthoor

Jan F Van Houdt

Praveen Raghavan

Stefan Cosemans

Anabela Veloso

Shairfe Muhammad Salahuddin

Edouard Giacomin

Dan Mocuta

Syed Muhammad Yasser Sherazi

Eric Beyne

Mustafa Badaroglu

Jan Craninckx

Jonathan Borremans

Aryan Afzalian

Geert Van Der Plas

Alessio Spessot

Lars-Ake Ragnarsson

Erik Jan Marinissen

Dimitri Linten

Zsolt Tokei

Tom Schram

Steven Demuynck

Christopher Wilson

Anshul Gupta

Raf Appeltans

Serge Biesemans

Jürgen Bömmels

Hyungrock Oh

Hendrik Fw Dekkers

Lynn Bos

Bilal Chehab

Victor Hugo Vega Gonzalez

The present disclosure relates to a method for forming a stacked transistor device comprising a lower NSHFET structure and an upper FinFET structure including: forming a fin structure comprising: a lower device sub-stack comprising a number of lower channel nanosheets, a middle insulating layer, an upper device sub-stack comprising an upper channel layer, and a capping layer; forming a process layer embedding the fin structure; subsequent to forming the process layer, removing the capping layer from the fin structure to define a gap exposing the upper device sub-stack; forming spacer layers on opposite side surfaces of the gap to form a reduced-width gap; splitting the upper channel layer by etching back an upper surface thereof via the reduced-width gap to form two upper channel fins; subsequent to forming the upper channel fins, removing the spacer layers; and thereafter: forming a gate structure; and forming source and drain regions for the lower channel nanosheets and the upper channel fins.

Method for forming a stacked transistor device

A standard cell semiconductor device is provided that includes a first and second FET device, each including: (i) a source body and a drain body, each including a common source or drain body portion and a set of source or drain prongs protruding from the common source or drain body portion, (ii) a set of channel layers, each channel layer extending between a pair of source and drain prongs, and (iii) a gate body including a common gate body portion and a set of gate prongs protruding from the common gate body portion.

Circuit cell for a standard cell semiconductor device

A FET device () is provided, the FET device including a substrate (), a source body (), a drain body () and a set of vertically spaced apart channel layers () extending between the source and drain body in a first direction along the substrate (), the source body () comprising a common source body portion () arranged at a first lateral side of the set of channel layers () and a set of vertically spaced apart source prongs () protruding from the common source body portion () in a second direction along the substrate (), transverse to the first direction, the drain body () comprising a common source body portion () arranged at the first lateral side of the set of channel layers () and a set of drain prongs () protruding from the common drain body portion () in the second direction; and a gate body () comprising a common gate body portion () arranged at a second lateral side of the channel layer (), opposite the first lateral side, and a set of gate prongs () protruding from the common gate body gate portion () in a third direction along the substrate (), opposite the first direction; wherein each channel layer () comprises a first side () and an opposite second side (), the first side arranged in abutment with a topside or an underside of a pair of source and drain prongs () and the second side () facing a gate prong ().

Field-effect transistor device

A multiport memory cell for register files is disclosed. Vertically stacked top and bottom tier of the memory cell are electrically interconnected through a pair of vias and comprise each an active device layer and a metal layer stack. The memory cell is partitioned to have a latching circuit and at least one write port located in the bottom tier and at least two read ports in the top tier. A word line trace for controlling the at least one write port is formed in the bottom tier metal layer stack and comprises two terminal sections and one intermediate section oriented perpendicularly to the terminal sections. The intermediate section is arranged between the pair of vias in a height direction of the memory cell.

Multiport memory cells including stacked active layers

According to an aspect there is provided a FET device. The FET device comprises a common source body portion and a set of source layer prongs protruding therefrom in a first lateral direction. First dielectric layer portions are arranged in spaces between the source layer prongs. The device further comprises a common drain body portion and a set of drain layer prongs protruding in the first lateral direction. Second dielectric layer portions are arranged in spaces between the drain layer prongs. The device further comprises a gate body comprising a common gate body portion and a set of gate prongs protruding therefrom in a second lateral direction opposite the first lateral direction. Each gate prong is formed intermediate a respective pair of first and second dielectric layer portions. The device further comprises a channel region comprising a set of channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer prongs. The channel layer portions are arranged in spaces between the gate prongs. There is also provided a method for forming a FET device.

FET device and a method for forming a FET device

According to an aspect of the present inventive concept there is provided 3D IC, comprising:

3D integrated count

In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure. Further, the method can comprise etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure.

Self-aligned contacts for walled nanosheet and forksheet field effect transistor devices

In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

Self-aligned contacts for nanosheet field effect transistor devices

3D integrated circuit

Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines, the multilevel layer comprising at least three levels forming a centerline level, an upper extension line level, and a lower extension line level the levels providing multilevel routing tracks in which the lines extend.

Integrated circuit with an interconnection system having a multilevel layer providing multilevel routing tracks and method of manufacturing the same

A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench.

Method for forming a buried metal line

A method of forming an interconnect structure for a standard cell semiconductor device is disclosed. In one aspect, the method includes forming metal lines along respective routing tracks, wherein forming the metal lines includes depositing, on a first dielectric layer covering the active regions of the cell, a metal layer and a capping layer on the metal layer; patterning the capping layer and the metal layer to form first and second capped off-center metal lines extending along first and second off-center tracks, respectively; forming spacer lines on sidewalls of the capped off-center metal lines; and embedding the spacer-provided capped off-center metal lines in a second dielectric layer. The method further includes patterning a set of trenches in the second dielectric layer. The set of trenches includes a center trench extending along a center track between the spacer-provided capped off-center lines, and a first and a second edge trench extending along first and second edge tracks, respectively, on mutually opposite outer sides of the spacer-provided capped off-center metal lines. The method further includes forming a center metal line in the center trench, and a first and a second edge metal line in the first and second edge trenches, respectively.

Standard cell device and method of forming an interconnect structure for a standard cell device

The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs. In one aspect, a semiconductor device comprises first and second sets of transistors comprising a pass transistor and a stacked complementary transistor pair of a lower transistor and an upper transistor, wherein first transistor comprises a semiconductor channel extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a second fin track parallel to the first fin track, and wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level, a first tall gate electrode forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and a first short gate electrode forming a gate for the first pass transistor and arranged along a second gate track, a second tall gate electrode forming a common gate for the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the second pass transistor and arranged along the first gate track, first and second contact arrangements forming a common drain contact for the transistors of the first set and the second set, respectively, and first and second cross-couple contacts extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.

Semiconductor device having stacked transistor pairs and method of forming same

The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.

Memory devices based on ferroelectric field effect transistors

A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.

Method of manufacturing a semiconductor device including the horizontal channel FET and the vertical channel FET

Growing community of inventors

Schaerbeek, Belgium

Julien Ryckaert