Lam Research Corporation

Imec Vzw

Katholieke Universiteit Leuven, Ku Leuven R&d

Katholieke Universiteit Leuven

Julien Mailfert

Saravanapriyan Sriraman

Mehmet Derya Tetiker

Andrew D Bailey, Iii

Ye Feng

Marcus Musselman

Yan Zhang

Sandip Halder

Philippe Leray

Werner Gillijns

Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

Method of etch model calibration using optical scatterometry

Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

Layout pattern proximity correction through fast edge placement error prediction

The disclosure relates to a method for verifying a printed pattern. In an example embodiment, the method includes defining sectors of at least a portion of the features in the reference pattern, determining a contour of the printed pattern, and superimposing the contour of the printed pattern on the reference pattern. The method also includes determining surface areas of sectors of the printed pattern that correspond to the sectors of the reference pattern and calculating one or more parameters as a function of at least one of the surface areas, the parameters being related to a single sector or to multiple sectors. The method additionally includes evaluating the parameters with respect to a reference value.

Method for verifying a pattern of features printed by a lithography process

The disclosure is directed to a method for designing a lithographic mask to print a pattern of structural features, wherein an OPC-based methodology may be used for producing one or more simulated patterns as they would be printed through the optimized mask. A real mask is then produced according to the optimized design, and an actual print is made through the mask. To evaluate the printed pattern and the PW on wafer more accurately, experimental contours are extracted from the CD-SEM measurements of the printed pattern. The verification of the mask is based on a comparison between on the one hand the contour obtained from the printed pattern, and on the other hand the intended pattern and/or the simulated contour. A direct comparison can be made between simulation and experiment, without losing all the pieces of info contained in each single CD-SEM picture.

Method for designing a lithographic mask

Growing community of inventors

Leuven, Belgium

Julien Mailfert