Stmicroelectronics (crolles 2) Sas

Tronics Microsystems S.a.

Tronic's Microsystems

Julien Cuzzocrea

Laurent-Luc Chapelon

Joël Collet

A MEMS device comprises a first layer (), a second layer () and a third layer () sealed together. A mobile structure () in the second layer () is defined by openings () in the second layer (). In the first layer (), there is at least one first-layer cavity () with an opening towards the mobile structure () of the second layer (). In the third layer (), there is at least one third-layer cavity () with an opening towards the mobile structure () of the second layer (). Therefore, the third-layer cavity () and the second layer () define a space within the MEMS device, A getter layer () arranged on a surface of said space. The getter layer () is preferably arranged on a surface of the second layer () and in particular, the getter layer () is arranged on a static part of the second layer (). Alternatively, the MEMS device has a third-layer cavity () with at least two recesses () and the getter layer () is arranged on a surface of the recesses ().

MEMS device with getter layer

An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.

Integrated circuit chip and fabrication method

An electrical connection structure for an integrated circuit chip includes a through via provided in a opening and a laterally adjacent void that are formed in a rear face of a substrate die. A front face of the substrate die includes integrated circuits and a layer incorporating a front electrical interconnect network. The via extends through the substrate die to reach a connection portion of the front electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via above the void. A local external protection layer may at least partly cover the electrical connection via and the electrical connection pillar.

A method is for formation of an electrically conducting through-via within a first semiconductor support having a front face and comprising a silicon substrate. The method may include forming of a first insulating layer on top of the front face of the first semiconductor support, fabricating a handle including, within an additional rigid semiconductor support having an intermediate semiconductor layer, and forming on either side of the intermediate semiconductor layer of a porous region and of an additional insulating layer. The method may also include direct bonding of the first insulating layer and of the additional insulating layer, and thinning of the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face.

Method for formation of an electrically conducting through via

Integrated-circuit chips are fabricated according to a process wherein weak portions are formed in a substrate wafer surrounding a plurality of locations. An integrated-circuit chip is defined at each location by destroying the weak portions so as to singulate integrated-circuit chips.

Process for fabricating integrated-circuit chips

Front-side integrated parts of integrated-circuit chips are produced at locations on a substrate wafer. The front-side parts have a front side. A support wafer having a bearing side is mounted with the bearing side on top of said front-side parts. The support wafer includes at least one weak surface layer. This weak surface layer is attached to the substrate wafer using a retaining adhesive. In one implementation, the weak surface layer is attached to a front surface of the wafer. In another implementation, the weak surface layer is attached to a peripheral edge of the wafer. After attaching the support wafer, back-side integrated parts of the integrated-circuit chips are produced on the substrate wafer. The weak surface layer is then destroyed so as to demount the support wafer from the substrate wafer.

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Grenoble, France

Julien Cuzzocrea