Taiwan Semiconductor Manufacturing Comp. Ltd.

Julie Huang

Mong-Song Liang

Chen-Jong Wang

Shing-Long Lee

Tse-Liang Ying

Chun-Yi Shih

Chung Hsin Fang

Eric Wang

A method of removing an etch-stop layer such as Si,N,from the vicinity of contact openings is described. A need for the removal of this material arises when the surface of the etch-stop layer is exposed during processing and the substrate is subjected to temperatures above 700&deg; C. Because of the high intrinsic interfacial stress residing in the Si,N,, the thermal impact causes cracks in the layer which emanate from the corners of the contact openings and travel, with branching, over a considerable distance from the opening. These cracks are prone to moisture adsorption and contamination which can compromise the reliability and performance of contacts. In addition, where contact openings are formed through insulating layers having an intermediate etch-stop layer, protrusions of the etch-stop layer occur within the contact opening because of un-even etching. These protrusions shadow the flux of subsequently deposited barrier materials into the opening, thereby forming weak spots along the contact walls. Timely removal the etch-stop layer around the contact opening eliminates these protrusions.

DRAM contact process by localized etch-stop removal

A method of removing an etch-stop layer such as Si.sub.3 N.sub.4 from the vicinity of contact openings is described. A need for the removal of this material arises when the surface of the etch-stop layer is exposed during processing and the substrate is subjected to temperatures above 700.degree. C. Because of the high intrinsic interfacial stress residing in the Si.sub.3 N.sub.4, the thermal impact causes cracks in the layer which emanate from the corners of the contact openings and travel, with branching, over a considerable distance from the opening. These cracks are prone to moisture adsorption and contamination which can compromise the reliability and performance of contacts. In addition, where contact openings are formed through insulating layers having an intermediate etch-stop layer, protrusions of the etch-stop layer occur within the contact opening because of un-even etching. These protrusions shadow the flux of subsequently deposited barrier materials into the opening, thereby forming weak spots along the contact walls. Timely removal the etch-stop layer around the contact opening eliminates these protrusions.

The present invention discloses a method for forming DRAM stacked capacitors by utilizing a densified oxide layer as an etch-stop for the wet etching process of an upper oxide layer in forming a contact hole for the stacked capacitor and thus, eliminating the need of a silicon nitride etch-stop layer and the occurrence of numerous processing difficulties normally observed in such stacked capacitor forming process. The lower oxide layer can be formed by a BPTEOS chemistry while the upper oxide layer can be formed by an ozone-TEOS chemistry.

Method for forming DRAM stacked capacitor

A structure for forming an ohmic contact to the drain of a MOSFET in a stacked capacitor DRAM cell is described. The contact is formed by making an opening in the upper cell plate of the cells capacitor and contacting the storage plate through this opening with a conductive plug, preferably a tungsten plug. The plug is formed concurrent with the conventional contact and first metal wiring processing of the DRAM. The contact is used in DRAM test arrays for characterizing the quality of MOSFET gate insulator as well as the performance characteristics of the MOSFET itself. Connection to the conductive plug is made with first metal wiring. The test structures can be built at any position within the array and since they are located above the polysilicon bitline/wordline structure, the metal connection lines for the contacts do not interfere with the structure of the test array itself other than the sacrifice of the test cell from the array. Multiple devices may be designated from anywhere in the array, and probe contacts may be conveniently located on the chip.

External contact to a MOSFET drain for testing of stacked-capacitor DRAMS

The present invention discloses a method for making low-topography buried capacitor including the steps of first depositing oxide layers, and then forming a small pre-contact hole by a dry etch method and a large contact hole by a wet etch method while using silicon nitride caps and sidewall spacers previously deposited on the word lines and on the bit lines as etch stop layers. A buried capacitor that has significantly improved topography can be fabricated in a semiconductor device.

Method for making low-topography buried capacitor by a two stage etching

A method is described which uses the differential etch behaviour of two different kinds of sequentially deposited silicon oxide layers in conjunction with controlled thicknesses and etching conditions to allow the etching of features such as via contact holes, oxide sidewalls, and crossover insulation edges to produce non-abrupt step height profiles for better edge coverage while still maintaining close adherence to minimum spacing design ground rules between adjacent features.

Method for edge profile and design rules control

A new method of forming an improved buried contact junction is described. Word lines are provided over the surface of a semiconductor substrate. A first insulating layer is deposited overlying the word lines. The first insulating layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate. A layer of tetraethoxysilane (TEOS) silicon oxide is deposited over the first insulating layer and over the semiconductor substrate within the opening. The TEOS layer is anisotropically etched to leave spacers on the sidewalls of the word lines and of the first insulating layer. A first layer of polysilicon is deposited overlying the first insulating layer and within the opening. The first polysilicon layer is doped with dopant which is driven in to form a buried contact junction within the semiconductor substrate under the opening. The first polysilicon layer is patterned to form a polysilicon contact overlying the buried contact junction wherein the mask used for the patterning is misaligned and wherein a portion of a TEOS spacer overlying the buried contact junction is exposed and wherein a portion of the first polysilicon layer other than that of the contact remains as residue. The first polysilicon layer residue is etched away wherein the exposed TEOS spacer protects the buried contact junction within the semiconductor substrate from the etching completing the formation of a buried contact in the fabrication of an integrated circuit.

Method of making buried contact in DRAM technology

Method of making an external contact to a MOSFET drain for testing of

An improved process for fabricating cylindrical capacitors for use in DRAMs is described wherein the silicon nitride etch stop layer is eliminated. The etch stop layer is normally used to halt etching during the formation of the dielectric cylinder that is used as a substrate on which the cylindrical electrode gets built. If etching is allowed to proceed, the underlying dielectric layer on which the cylinder rests will also be removed. In place of the etch stop layer, the present invention calls for two dielectric layers that have generally similar properties in other respects but substantially different etch rates. For the fast etching dielectric, O.sub.3 TEOS is used while, for the slow etching dielectric, BPTEOS is used. When etched in 10:1 BOE a differential etch rate of about 10 times is obtained so that formation of a O.sub.3 TEOS cylindrical substrate can be completed without significantly eroding the underlying BPTEOS support layer.

Method for forming a cylindrical capacitor

A new method of avoiding the formation of a polysilicon stringer along the slope of the bit line contact hole edge is described. A gate electrode and associated source/drain regions are formed in and on the surface of a semiconductor substrate wherein the bit line contact is to be formed adjacent to the gate electrode. First spacers are formed on the sidewalls of the gate electrode. A first insulating layer over the gate electrode adjacent to the bit line contact has a first slope. Second spacers on the sidewalls of the first insulating layer adjacent to the bit line contact have a second slope less than the first slope. A second polysilicon layer is deposited overlying the gate electrode and patterned. A first dielectric layer and a third polysilicon layer is deposited overlying the second polysilicon layer. The third polysilicon layer is etched away where the bit line contact is to be formed. The gentler slope of the second spacers allows the third polysilicon layer to be etched away without leaving stringers. A bit line contact opening is etched through a second dielectric layer to the underlying semiconductor substrate wherein the bit line contact opening is separated from the third polysilicon layer by a thickness of the second dielectric layer. A fourth polysilicon layer is deposited within the contact opening to form the bit line contact.

Method for forming dielectric spacer to prevent poly stringer in stacked

A method for fabricating a dual-gate oxide for memory with embedded logic has been achieved. The method is described for forming a thin gate oxide for the peripheral circuits on a DRAM device, while providing a thicker oxide for the memory cells having a boosted word line architecture. The method avoids applying photoresist directly to the gate oxide, and thereby prevents contamination. A first gate oxide is formed on the device areas on the substrate. A first polysilicon layer is deposited and patterned leaving portions over the memory cell areas. The first gate oxide is removed over the peripheral device areas, and is replaced by a thinner second gate oxide. A second polysilicon layer is deposited and patterned to remain over the peripheral device areas. The first and second polysilicon layers, having essentially equal thicknesses, are coated with an insulating layer. The FET gate electrodes for both the peripheral and memory cell areas are simultaneously patterned from the first and second polysilicon layers to complete the DRAM structure up to and including the gate electrodes.

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Hsin-chu, Taiwan

Julie Huang