International Business Machines Corporation

Tessera Intellectual Properties, Inc.

Julie C Biggs

Sarah Huffsmith Knickerbocker

Kamalesh K Srivastava

Tien-Jen Cheng

Jonathan H Griffith

David E Eichstadt

Roger Allan Quon

Subhash Laxman Shinde

William Edward Sablinski

Wolfgang Sauter

Kevin Shawn Petrarca

Richard Paul Volant

Randolph F Knarr

Lisa A Fanti

Roger A Quinn

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.

Forming robust solder interconnect structures by reducing effects of seed layer underetching

A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Method of forming a bond pad on an I/C chip and resulting structure

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

Method for forming robust solder interconnect structures by reducing effects of seed layer underetching

I/C chip suitable for wire bonding

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Wappingers Falls, NY, United States of America

Julie C Biggs