International Business Machines Corporation

Julie Ann Rosser

Robert Alan Cargnoni

Charles Francis Marino

Samuel I Ward

Jeremy T Hopkins

Gary Alan Gorman

A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The processor distributes data on-ramps and data off-ramps across the data lanes of a data trunk of the primary interconnect trunk to enable communication with compute elements and other structures both on-chip and off-chip.

Information handling system including a multiple compute element processor with distributed data on-ramp data-off ramp topology

Spare cells are placed in an IC design using stability values associated with logic cones of the design. A desired spare cell utilization rate is assigned to a cone based on its stability value, and an actual spare cell utilization rate for the cone bounding box is calculated. If the actual utilization rate is less than the desired utilization rate, additional spare cells are inserted as needed to attain the desired utilization rate. The stability value is provided by a logic or circuit designer, or derived from historical information regarding the logic cone in a previous design iteration. Spare cells are placed for each logic cone in the design until a global spare cell utilization target is exceeded. The spare cell placement method can be an integrated part of a placement directed synthesis which is followed by early mode padding and design routing.

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Julie Ann Rosser