Arm Limited

Julian Katenbrink

Daren Croxford

Guy Larri

The present disclosure relates to a method of operating a graphics processing system for providing frames over communication channel in a communication network, the graphics processing system being configured to process data for an application executed thereon to render frames for the application to be output for transmission over the communication channel to a client device, the method comprising: determining network characteristics of the communication network and/or server characteristics of the server; adaptively selecting a first prediction method from a plurality of prediction methods to be used for displaying frames based on the determined network characteristics and/or server characteristics; generating a plurality of frames based on the first prediction method; and selectively providing, based on the first prediction method, one or more output frames from the plurality of frames to the application to be output for transmission over the communication channel.

Graphics processing system

An apparatus has first-in, first-out (FIFO) buffer circuitry to transfer data from a source domain to a sink domain across a clock domain boundary. The FIFO buffer circuitry has data transfer circuitry to store the data to be transferred across the clock domain boundary; and source and sink domain data transfer control circuitry to maintain respective state vectors indicative of a state of the FIFO buffer circuitry in the respective domain. At least one of the source domain transfer control circuitry and the sink domain transfer control circuitry is operable to perform a multi-item transfer to transfer two or more data items in a single clock cycle of a respective domain by placing the data items into, or reading the data items from, respective data storage elements; and advancing a state vector of the respective domain by two or more state vector encodings in the single clock cycle.

First-in, first-out buffer

An apparatus has first-in, first-out buffer circuitry to transfer data from a source domain to a sink domain across a clock domain boundary. The FIFO buffer circuitry has data transfer circuitry; source domain and sink domain data transfer control circuitry to maintain state vectors indicative of a state of the FIFO buffer circuitry in the respective domain; and synchronisation circuitry in each of the source domain and the sink domain to stabilise a signal received from the other of the source domain and the sink domain and to store the received state vector. The synchronisation circuitry is clock-gated by an enable signal and the synchronisation circuitry is responsive to a change in the state of the FIFO buffer circuitry in the respective domain to advance the respective state vector by controlling the enable signal to enable output of elements of the received state vector.

Growing community of inventors

Ely, United Kingdom

Julian Katenbrink