Other

Perceptia IP Pty Ltd

Perceptia Devices, Inc.

Perceptia Devices Australia Pty Ltd

Globalfoundries Inc.

Perceptia Devices IP Pty Ltd

Unsw Innovations

Julian Jenkins

André Grouwstra

Torsten Lehmann

Timothy Robins

Stephen Allott

James Paul Koeppe

Tara Hamilton

Andrew Nicholson

Artemij Iberzanov

Methods and circuits are provided for range extension of a phase-locked loop (PLL). The PLL uses a phase subtractor with a limited unextended range. It also includes first and second registers and combinatorial logic. The phase subtractor calculates the current phase difference. The first register stores the previous phase difference. The combinatorial logic determines, from the current phase difference and the previous phase difference, if a range excursion occurs, and if it is upward or downward. When an upward excursion occurs, the value in the second register is incremented. When a downward excursion occurs, the value of the second register is decremented. The bits in the second register are combined with the bits of the current phase difference to obtain an extended current phase difference.

PLL with phase range extension

A PLL has a frequency comparator that is active during lock-in. It outputs a signal related to the difference between the oscillator frequency and a target frequency. It captures an initial phase and observes change in phase relative to the initial phase. Two ways of capturing the initial phase are provided. The frequency comparator can provide input signals for the loop filter and make the PLL act as a frequency-locked loop during lock-in. Alternatively, it can provide input signals for a search controller that may perform a binary or other search. The frequency comparator may wait one or more cycles of the reference clock signal to reduce noise, or it may set a threshold to eliminate some noise. It may signal that the oscillator frequency equals the target frequency when the threshold has not been exceeded after a timeout. The search controller may directly or indirectly control the PLL's oscillator.

PLL with Lock-in Frequency Controller

A PLL includes a controlled oscillator, a phase accumulator to measure the controlled oscillator output phase, a phase predictor to calculate the required output phase, and a phase subtractor to calculate the phase difference or phase error. The phase accumulator includes a counter whose output sequence changes only one bit per counted controlled oscillator output cycle, such as a Gray counter. It further includes a register or latches, which sample(s) the counter output value upon receiving a reference clock pulse. The latches output value represents the measured phase. A binary encoder, such as a Gray-to-binary converter, may translate the measured phase to a binary number. The phase accumulator may further include a delay line, second latches, and a delay line decoder to measure a fractional part of the phase. A calibration feedback loop may keep the number of delay line steps per output clock pulse known and stable.

Phase accumulator with improved accuracy

A PLL has a controlled oscillator with a limited frequency range. It has a phase accumulator and a phase predictor whose ranges are limited to a value K related to their bit width. K is less than the ratio of the maximum output frequency and the minimum reference frequency. The PLL locks the output frequency to a value higher than the FCW times the reference frequency. The PLL includes a means for setting the output frequency to a target frequency before achieving final lock. The PLL may have a lock detector. After acquiring lock, the PLL may reduce the bit width and K value, for example by cutting power to or switching off some of the bits, or by switching off slow counters in a multi-counter system.

PLL with beat-frequency operation

A PLL includes a controlled oscillator, a phase accumulator to measure the controlled oscillator output phase, a phase predictor to calculate the required output phase, and a phase subtractor to calculate the phase difference or phase error. The phase accumulator includes a fast counter and a low-power counter, and two sets of corresponding latches. The fast counter counts cycles of the controlled oscillator clock signal, and the low-power counter counts carry signals from the fast counter. The low-power counter represents one or more most significant bits of the integer part of the measured phase, and the fast counter represents the remaining bits. The phase accumulator may further include a delay line, second latches, and a delay line decoder to measure a fractional part of the phase. A calibration feedback loop may keep the number of delay line steps per output clock pulse known and stable.

Power-saving phase accumulator

The present disclosure relates to an injection locked oscillator system and processes and, more particularly, to structures and processes for generating an inductor-less frequency multiplier using injection locking and histogram calibration with a back-gate process. The structure includes injection locked oscillator (ILO) system which is structured to provide a local oscillator (LO) and a Digitally Controlled Oscillator (DCO) or Voltage Controlled Oscillator (VCO) frequency which is not harmonically related by an integer multiple to an output frequency.

Injection locked oscillator system and processes

A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control signal that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. A first sleep mode control signal blocks a reference clock and feedback of the oscillator clock to the counter. It may also freeze loop filter parameters and block the output clock. A second sleep mode control signal may stop the oscillator.

Fractional-N PLL with sleep modes

A voltage or current regulator has a power DAC and ADC in a negative feedback loop, locked to a reference voltage or current. The ADC may have one or more parallel comparators followed by one or more parallel filters. The regulator may include a multiplexer to select between filter output signals and to forward the selected signal to the power DAC. The regulator may receive power management mode control codes to modify filter behavior and/or to select between multiple parallel filters. By modifying the loop behavior, the regulator is able to swiftly change between power management modes supporting different power level and noise profiles. Regulators with a single comparator can lock the output to a single reference voltage or current. Regulators with two comparators can regulate the output to vary within a range limited by an upper and a lower reference voltage or current.

Regulator circuits and methods

A block of logic gates has MOS transistors whose body terminals are connected with a body voltage rail and whose source terminals are connected with a logic reference voltage rail. The logic reference voltage rail is connected to the body voltage rail via a resistor. The resistor creates a negative feedback loop for leakage currents that stabilizes a reverse body bias voltage and reduces the influence of temperature, voltage, and process variations. The block may be NMOS, PMOS, or CMOS. In the case of CMOS, there are two body voltage rails, powered by a voltage source, two logic reference voltage rails, and two resistors. The reverse body bias voltages over the two resistors may be stabilized by decoupling capacitors. The two resistors may be trimmable. The resistors may be calibrated such that leakage currents are at a minimum value and the logic gates can switch just fast enough.

Circuits and methods for lowering leakage in ultra-low-power MOS integrated circuits

A comparator circuit has a sense amplifier with a differential pair, a voltage excursion limiter, and a switch. The differential pair receives two analog input signals. Its differential outputs operate at a common mode voltage approximately half the supply voltage. The voltage limiter is coupled with one of the differential pair outputs. A capacitor may store comparison results. The switch energizes the differential pair and the voltage excursion limiter during a first phase of a clock, and de-energizes them during a second phase of the clock. During this phase, the comparator may provide the stored comparison result to an amplifier with positive feedback.

High-speed clocked comparators

A delay line is constructed by combining a phase generator and a fabric. The phase generator splits a digital input signal in multiple incrementally delayed versions, which are input to the fabric. The fabric has an array of node filters. Inputs of filters in the first array column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form a filter output signal. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other array rows. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements.

Delay line

A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control code that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. The PLL may be implemented with dedicated or off-the-shelf circuitry, in an FPGA, or with a programmable processor. A tangible non-transitory memory may hold an associated software instructions for fractional-N phase locking.

Low-power fractional-N PLLs

A phase-locked loop (PLL) has at least two parallel loops. The loops share an oscillator, a counter connected with the oscillator, a multiplexer, and a loop filter. Each loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The loop forwards the integer difference between the sampled phase and the predicted phase to the multiplexer, which selects one of the loops and provides the difference to the loop filter. Loops that are not selected use a monitor-and-adjust function to keep the difference in track with the difference of a selected loop. Loops may provide a loop sleep function and the PLL may also provide an oscillator sleep function.

Multiple-loop fractional-N PLL with hitless switching

A phase-locked loop (PLL) has a primary loop (with a reference clock) and a secondary loop (with a stable reference clock). The secondary loop may include a fractional-N PLL, and may include a secondary loop filter, oscillator, output clock counter, and phase predictor using a rational secondary frequency control word (FCW). The primary loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a primary fractional-N FCW to calculate a predicted phase as an integer number. The primary loop forwards the integer difference between the sampled phase and the predicted phase to a primary loop filter, which outputs the secondary FCW. The primary loop filter has a much lower bandwidth than the secondary loop filter. The PLL may have multiple primary loops, with a hitless switching function. A primary loop may have sleep mode. The PLL may also provide an oscillator sleep function.

Fractional-N jitter attenuator

An amplifier calibration system has a calibration controller, a comparator coupled between an amplifier to be tested and the calibration controller, and an analog test signal generator driven by the calibration controller and coupled to the amplifier input. The system applies a cycle of analog tests to the amplifier input. The cycle has an upward path and a downward path. The upward path includes three signal levels: lowest, medium low, and medium high. The downward path includes: highest, medium high, and medium low. The comparator determines successive polarities of the amplifier's responses to the cycle of analog tests. Based on the polarities, the system determines amplifier characteristics, and calibrates amplifier parameters to change the amplifier characteristics to desired values. Characteristics may include hysteresis, offset, input range values, and other amplifier specifications.

Growing community of inventors

Kurraba Point, Australia

Julian Jenkins