Texas Instruments Corporation

Julian Becker

Eduardas Jodka

Stefan Dietrich

Carsten Stoerk

Joerg Kirchner

Puneet Sareen

Christian Harder

A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator circuit, a second input coupled to the output of the off-time timer circuit and an output coupled to a control terminal of the transistor.

Seamless DCM-PFM transition for single pulse operation in DC-DC converters

A gate driver for a high-side NMOS power transistor in a DC/DC boost converter includes first and second switches coupled in series between an output pin and the gate of the high-side transistor. A third switch is coupled between the gate and a switch-node between the high-side and low-side transistors, the switch node also being coupled to an input pin. Fourth and fifth switches are coupled in series between the output pin and a clamp pin. Sixth and seventh switch are coupled in series between the output pin and a ground pin. First and second bootstrap capacitors have respective first terminals coupled to a first node between the first and second switches. The first capacitor has a second terminal coupled to a node between the fourth and fifth switches; the second capacitor has a second terminal coupled to a node between the sixth and seventh switches.

Process of operating switched-mode DC/DC converter having a bootstrapped high-side driver

A power supply system can include at least one power switch to generate an output current based on an input voltage in response to a switching signal to generate an output voltage. A feedback system generates a feedback current based on the output voltage. A mode detector generates a control current associated with the output current based on the feedback current and selects between a pulse-width modulation (PWM) mode and a pulse mode based on an amplitude of the control current. The PWM mode is associated with a sequential on-time and off-time of the at least one power switch, and the pulse mode is associated with adding an idle time between the on-time and the off-time of the at least one power switch based on the switching signal. A gate driver system generates the switching signal based on the mode.

Power supply system with pulse mode operation

Switched-mode DC/DC converter having a bootstrapped high-side driver

A switch-node rising edge detection circuit is provided for a switched-mode DC/DC boost converter. A high-side gate-driver couples a gate of the high-side NMOS power transistor to either a first terminal of a bootstrap capacitor or the switch-node. The detection circuit includes an AND gate that receives an activation signal on a first input and provides a switching signal to the high-side gate-driver. A PMOS transistor is coupled in series with an inverter between the first terminal of the bootstrap capacitor and a second input of the AND gate. The inverter receives supply voltages from the first terminal of the bootstrap capacitor and the switch-node. The gate of the PMOS transistor receives the activation signal. An NMOS transistor is coupled between an output voltage and a node between the PMOS transistor and the inverter. A gate of the NMOS transistor is coupled to the bootstrap capacitor's first terminal.

A level shifter with reduced propagation delay. A level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to an input terminal of the first transistor. The first capacitor includes a bottom plate coupled to an input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor, and an output terminal coupled to the first signal output node.

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Freising, Germany

Julian Becker