Cadence Design Systems, Inc.

Julia Pinheiro De Oliveira

Tulio Paschoalin Leao

Lucas Martins Chaves

Petros Daniel Fernandes De Medeiros Félix

Andrei Dos Santos Silva

Arthur Ribeiro Araujo

Pablo Nunes Agra Belmonte

A formal verification EDA application can be configured to receive a circuit design of an IC chip. The circuit design of the IC chip comprises a set of properties for the IC chip and constraints for the IC chip. The formal verification EDA application generates an array of CNF files based on the circuit design of the IC chip. Each CNF file can include a Boolean expression that characterizes a selected property of the set of properties and data fields characterizing initial states for literals in the Boolean expression and the constraints of the IC chip. The formal verification application can also be configured to output the array of CNF files to a hardware prototyping platform. The hardware prototyping platform can be configured to execute a hardware instantiated SAT solver for the Boolean expression in each CNF file in the array of CNF files.

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Belo Horizonte, Brazil

Julia Pinheiro De Oliveira