General Electric Company

Juka Mikko Hakkarainen

Chung-Yih Ho

Nga Cheung Lee

A communications unit configured to be implemented in an ASIC environment utilizes only a small amount of chip surface area and requires a minimum number of pins. The unit operates asynchronously with respect to the ASIC internal clock so that communications can occur independent of such internal clock. In one embodiment the communications unit includes a controller coupled to a shift register via a data bus. Pin connections to the controller include a request line REQ, an input/output control line I/O (or INOUT), an acknowledgement line ACK, an external clock line EXTCLK, and a data line DATA. The shift register also is coupled, via a data bus, to a memory module, e.g., a RAM. An ASIC processor is coupled to the controller, shift register and memory module via control lines.

On-chip communication circuit and protocol for microcontroller-based

Shift register having latch cell operable in serial-in/parallel-out and

An input signal buffer amplifier that has a high gain and a low offset voltage is implemented as an integrated circuit (IC) along with other components that perform further processing on an input signal. In one embodiment, the buffer amplifier includes first and second operational amplifiers (op amps). Voltage divider resistors R1 and R2 are connected in series between a positive voltage supply rail and a ground rail of the IC. The positive input terminal of the second op amp is electrically connected to a node between resistors R1 and R2. A feedback loop is established from the output of the second op amp to its negative terminal. The negative terminal of the first op amp is connected to a node between a series-connected input resistor and feedback resistor. The positive input terminal of the first op amp is connected to a node between series-connected voltage divider resistors R3 and R4 which are connected across the output of the second op amp and the ground rail. The first operational amplifier generates an output voltage signal VI+ and the second operational amplifier generates an output voltage signal VI-.

High gain, low offset input amplifier

An analog memory unit that can be implemented, at least in part, on an application specific integrated circuit (ASIC), utilizes at least the ASIC arithmetic logic unit (ALU) to enhance performance and to generate and store an accurate measure of power line thermal status. The memory unit includes an analog-to-digital (A/D) converter for converting an input analog signal from a parallel R-C circuit to a digital signal and a scaler for scaling the digital signal from the A/D converter to within a range acceptable for further processing. The memory unit also includes an arithmetic logic unit (ALU) which receives input signals from the scaler and from a digital thermal memory. The input signal supplied to the ALU from the digital thermal memory is a four bit (digital) value proportional to the measured actual thermal status of the subject power line. The output of the ALU is connected to the input of latches which latch, or store, the digital signal produced by the ALU. The ALU output signal is representative of the difference between charge on the R-C circuit and the most recently measured actual thermal status of the power line. The latches are connected to a digital-to-analog converter which has its output connected to the input of the A/D converter and to the R-C circuit.

Growing community of inventors

Coconut Grove, FL, United States of America

Juka Mikko Hakkarainen