Micrel, Incorporated

Faraday Technology Corporation

Sct Incorporated

Sct Technology, Ltd.

Verbaltek, Inc.

Juinn-Yan Chen

Eric Li

Shang-Kuan Tang

Shean-Yih Chiou

Wei-Kang Cheng

Yi Zhang

Wei-Gian Chen

WeiHao Chang

San-Chieh Chou

Zuoqin Wang

Josephine Chang

Yoon Kim

Raymond Ho

Zhenchao Liu

James Pan

A method for motion blur in an LED display system includes the steps of connecting an LED display panel to a driver circuit; sending, from a transmitter, image data in a plurality of image frames at a predetermined frame rate and a predetermined refresh rate to the driver circuit, wherein each of the plurality of image frames has a frame time period (T) comprising a plurality of refresh time periods (T); outputting a driving current in the driver circuit to drive the LED display; and turning off the driving current for a period of time (T). Tbridges two adjacent frame time periods. The value of Tcan be determined according to a viewer of persistence of vision or by calibrating the LED display.

System and method for reducing motion blur for LED display

A method for generating fractional PWM pulses to drive an light emitting device includes generating multiphase clock signals using a multiphase PLL or DLL includes the steps of generating a plurality of phases of PWM pulses that correspond to a number of phases of the multiphase clock signals, selecting two or more phases amongst the plurality of PWM pulses, performing logic operations of the selected phases of PWM pulses to generate fractional PWM pulses, and generating a driving current using the fractional PWM pulses in a current source. The light emitting device is can be an LED display comprising an LED array having a plurality of channels and a plurality of scan lines. The driving current drives LEDs in one of the plurality of channels.

Fraction PWM with multiple phase display clock

An LED display device includes a transmitter having a memory and a pixel mapping table, a plurality of first receivers coupled to the transmitter, a plurality of second receiver modules, and a plurality of LED driver groups. A unique address is assigned to a data packet with a use of the pixel mapping table. The data packet has a set of field information and the set of field information includes the unique address. Each of the second receiver modules is coupled to at least one of the first receivers and includes a plurality of second receivers. None of the plurality of second receivers comprises a pixel mapping memory. Each of the LED driver groups is coupled to one of the plurality of second receivers and includes a plurality of LED drivers.

LED display device and method for operating the same

This disclosure describes an LED display device. The LED display device includes a transmitter having a memory and a pixel mapping table, a plurality of first receivers coupled to the transmitter, a plurality of second receiver modules, and a plurality of LED driver groups. A unique address is assigned to a data packet with a use of the pixel mapping table. The data packet has a set of field information and the set of field information includes the unique address. Each of the second receiver modules is coupled to at least one of the first receivers and includes a plurality of second receivers. None of the plurality of second receivers comprises a pixel mapping memory. Each of the LED driver groups is coupled to one of the plurality of second receivers and includes a plurality of LED drivers.

This disclosure describes an LED display device. The LED display device includes a transmitter, a plurality of first receivers coupled to the transmitter, a plurality of second receiver modules, wherein each of the second receiver modules is coupled to at least one of the first receivers and comprises a plurality of second receivers, a plurality of LED driver groups, each of the LED driver groups coupled to at least one of the second receivers and having a plurality of LED drivers, and a transformerless wire link connecting the plurality of first receivers to the plurality of second receiver modules, or the transformerless wire link connecting adjacent receivers of the plurality of second receivers therebetween.

A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit implements a binary jump method and an operating curve is selected when the operating curve has an output frequency meeting the target frequency with the control voltage being within a first voltage range being a narrowed and centered voltage range within the control voltage range.

PLL frequency synthesizer with multi-curve VCO implementing closed loop curve searching

A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to perform a closed loop curve search operation to select one of the operating curves in the multi-curve VCO and to perform a curve tracking operation using the selected operating curve, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current during the curve tracking operation.

PLL frequency synthesizer with multi-curve VCO implementing closed loop curve searching using charge pump current modulation

A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current value after an operating curve is selected.

A multi-modulus divider includes a chain of n dual modulus divider cells in cascade and connected in a ripple configuration where the last (n-k) of the divider cells are state-parked dual modulus divider cells. The state-parked dual modulus divider cells are forced to a given logical state when the divider cell is bypassed. The state-parked dual modulus divider cells ensure that the multi-modulus divider can change between different number of cells without clock glitches or clock errors. The multi-modulus divider is therefore capable of achieving a wide division range with seamless transition between division ratios.

Wide range multi-modulus divider in fractional-N frequency synthesizer

A method for designing a noise shaper with a single loop distributed feedback delta-sigma modulator includes following steps: (a) determining a delta-sigma modulator comprising a plurality of parameters according to an order of the noise shaper; (b) deriving a noise transfer function comprising a plurality of coefficients corresponding to the parameters of the delta-sigma modulator according to the delta-sigma modulator; (c) determining a high-pass filter corresponding to the delta-sigma modulator according to a default requirement; (d) solving the coefficients of the noise transfer function according to the high-pass filter; and (e) feeding the solved coefficients in step (d) into the parameters of the delta-sigma modulator for completing the noise shaper.

Method for designing a noise shaper with a single loop distributed feedback delta-sigma modulator

A sigma-delta modulated discrete time oscillator. The sigma-delta modulated discrete time oscillator comprises a synchronous counter and a sigma-delta modulator. The sigma-delta modulator operating in a first clock receives a control signal to generate a divider pattern output. The control signal provides a DC value for the frequency of the first clock. The divider pattern comprises a plurality of numbers, values of which are synchronous with the rate of the first clock. The synchronous counter operates in a second clock. In the synchronous counter, the second clock is divided by the divider pattern to generate the first clock. The frequency of the second clock is much higher than the frequency of the first clock.

Sigma-delta modulated discrete time oscillator

A clock analyzer includes an input port for receiving a reference clock signal from an external source, a plurality of functionally identical delay cells for delaying the reference clock signal and generating a plurality of delayed clock signals, each delayed clock signal being delayed by a unique number of delay cells, and at least one comparator for comparing the reference clock signal to the plurality of delayed clock signals and choosing a selected clock signal from the plurality of delayed clock signals that at least partially overlaps the reference clock signal.

Self-calibrating clock generator for generating process and temperature independent clock signals

A sigma-delta modulator. The sigma-delta modulator comprises an integrator, a first quantizer, a dither generator and an adding device. An input terminal of the first quantizer and an input terminal of the dither generator are coupled to an output terminal of the integrator. The first quantizer generates a first random signal. The dither generator comprises a second quantizer for generating a second random signal, an input terminal thereof coupling to the output of the integrator; a random sequencer for receiving the first random signal and the second random signal to produce a third random signal output; and an attenuator for attenuating the third random signal to produce a dither signal to output. The dither signal is added to an input terminal of the integrator by the adding device.

Idle channel tone and periodic noise suppression for sigma-delta modulator using feedback-quantizer

An accurate speech recognition system capable of rapidly processing greater varieties of words and operable in many different devices, but without the computational power and memory requirements, high power consumption, complex operating system, high costs, and weight of traditional systems. The utilization of individual letter utterances to transmit words allows voice information transfer for both person-to-person and person-to-machine communication for mobile phones, PDAs, and other communication devices. This invention is an apparatus and method for a speech recognition system comprising a microphone, front-end signal processor for generating parametric representations of speech input signals, a pronunciation database, a letter similarity comparator for comparing the parametric representation of the input signals with the parametric representations of letter pronunciations, and generating a sequence of associations between the input speech and the letters in the pronunciation database, a vocabulary database, a word similarity comparator for comparing an aggregated plurality of the letters with the words in the vocabulary database and generating a sequence of associations between them, and a display for displaying the selected letters and words for confirmation.

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Fremont, CA, United States of America

Juinn-Yan Chen