Sun Microsystems, Inc.

Altera Corporation

Juin-Yeu Lu

Renxin Xia

Chaiyasit Manovit

Sudheendra G Hangal

Durgam Vahia

Yi Gao

Systems and methods for flexibly configuring one or more intellectual property (IP) blocks of a programmable logic device are described. The methods include configuring and operating a first portion of the programmable logic device before configuring a remaining portion of the programmable logic device. By operating the first portion before configuring the remaining portions, various timing constraints including power-up timing constraints can be met by the programmable logic device.

Systems and methods for flexibly configuring a programmable logic device

A system and method for verifying a memory consistency model for a shared memory multiprocessor computer systems generates random instructions to run on the processors, saves the results of the running of the instructions, and analyzes the results to detect a memory subsystem error if the results fall outside of the space of possible outcomes consistent with the memory consistency model. A precedence relationship of the results is determined by uniquely identifying results of a store location with each result distinct to allow association of a read result value to the instruction that created the read result value. A precedence graph with static, direct and derived edges identifies errors when a cycle is detected that indicates results that are inconsistent with memory consistency model rules.

Shared memory multiprocessor memory model verification system and method

Growing community of inventors

Campbell, CA, United States of America

Juin-Yeu Lu