Industrial Technology Research Institute

Juin-Ming Lu

Yao-Hua Chen

Jing-Jia Liou

Chih-Tsun Huang

Hsun-Lun Huang

Chun-Hung Lai

Yeong-Jar Chang

Hsin-Lung Wu

Chun-Chen Chen

Che-Wei Hsu

Ming-Der Shieh

Shau-Yin Tseng

Chung-Ho Chen

Liang-Chia Cheng

Mao-Yin Wang

Jai-Ming Lin

Jiung-Yao Huang

I-Hsuan Lu

Tai-Hua Lu

Ming-Chih Tung

Wan-Shan Hsieh

Heng-Yi Chen

Chen-Chieh Wang

Ya-Ting Shyu

Arthur Marmin

Yen-Fu Chang

Ting-Shuo Hsu

Mei-Ling Chi

Jih-Sheng Shen

Chun Wei Chen

Hsu-Yao Huang

Wei-Shiang Lin

Yu-Xiang Yen

Bo-Xuan Zhu

A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval.

Processing elements array that includes delay queues between processing elements to hold shared data

A neural network (NN) processing method is provided. An AI (artificial intelligence) compiler code of an AI compiler is transformed to a garbled circuit code by performing following steps. A circuit graph of a garbled circuit having logic gates corresponding to the garbled circuit code is sent to an electrical device by a server. Key codebooks for candidate gates corresponding to each logic gate are creating by the electrical device. Garbled truth tables for the candidate gates corresponding to each logic pate are generated and transmitted to the server by the electrical device through using OT (Oblivious Transfer) protocol. A target garbled truth table of each logic gate is generated by the server. Afterward, an NN model is encrypted according to the key codebooks by the electrical device and a compiled NN model of an encrypted NN model are generated by the server.

Neural network processing method and server and electrical device therefor

An adaptive learning power modeling method includes: sampling at least one of a plurality of network components to form a power consumption evaluation network according to at least one parameter within a parameter range; evaluating a predictive power consumption of a to-be-measured circuit by the power consumption evaluation network; training and evaluating an actual power consumption and the predictive power consumption of the to-be-measured circuit by the power consumption evaluation network to obtain an evaluation result; and performing training according to the evaluation result to determine whether to change the power consumption evaluation network.

Hardware structure aware adaptive learning based power modeling method and system

A DNN hardware accelerator and an operation method of the DNN hardware accelerator are provided. The DNN hardware accelerator includes: a network distributor for receiving an input data and distributing respective bandwidth of a plurality of data types of a target data amount based on a plurality of bandwidth ratios of the target data amount; and a processing element array coupled to the network distributor, for communicating data of the data types of the target data amount between the network distributor based on the distributed bandwidth of the data types.

Deep neural networks (DNN) hardware accelerator and operation method thereof

An image classification system includes a storage device, a computing device and a first processing device. The storage device stores a plurality of pseudo-centroid datasets, wherein the pseudo-centroid datasets correspond to a plurality of units of first image dataset, and the number of pseudo-centroid data points of each of the pseudo-centroid datasets is much smaller than the number of data points of each of the units of first image dataset. The computing device receives the second image data and computes a plurality of feature values of the second image data. The first processing device receives the feature values and the pseudo-centroid datasets, and compares the feature values with the pseudo-centroid data points to identify and classify the second image data.

Image classification system and method

Disclosed are a timing estimation method and a simulator. The method is applied to a function verification model. In the method, the model issues a first access issue at a first time point; receives a first response to the first access issue from the bus at a second time point; calculates a delay time between the first and second time points; determines whether the delay time is longer than or substantially equal to a transmission time corresponding to the first access issue; issues a second access issue if yes; and issues the second access issue in a compensation time counting from the second time point if not. The compensation time is not longer than the difference between the transmission time and the delay time.

Timing esimation method and simulator

An embodiment of a thermal estimation device including a temperature model generator, a temperature gradient calculator, and a thermal sensing analyzer is disclosed. The temperature model generator generates a temperature model based on an initial power consumption, an initial area and an initial coordination of a circuit module. The temperature gradient calculator substitutes at least one of a testing area, a testing power or a testing coordinate of the circuit module into the temperature model for correspondingly estimating an temperature estimation function. The thermal sensing analyzer differentiates the temperature estimation function. When an absolute value of a differential result of the temperature estimation function resulted from a constant is closest to zero or is zero, outputting the constant as an optimized parameter.

Thermal estimation device and thermal estimation method

A power consumption estimation method is applied to an image with N rows of pixels, and comprises a pixel estimation procedure comprising performing an estimation sub-procedure pixel by pixel for each of a plurality of pixels in one row of the N rows of pixels to obtain a plurality of pixel energy consumption values respectively corresponding to the plurality of pixels in said one row of the N rows, and obtaining a row power consumption value corresponding to said one row of the N rows according to the plurality of pixel energy consumption values. The estimation sub-procedure comprises obtaining pixel content information corresponding to one of the plurality of pixels, and determining the pixel energy consumption value according to the pixel content information. The pixel energy consumption value indicates pixel energy consumption generated by performing a predetermined image processing procedure for said one of the plurality of pixels.

Power consumption estimation method and power consumption estimation apparatus

A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.

Memory transaction-level modeling method and system

A scheduling method is provided. The method includes: recording a next instruction and a ready state of each thread group in a scoreboard; determining whether there is any ready thread group whose ready state is affirmative; determining whether a load/store unit is available, wherein the load/store unit is configured to access a data memory unit; when the load/store unit is available, determining whether the ready thread groups include a data access thread group, wherein the next instruction of the data access thread group is related to accessing the data memory unit; selecting a target thread group from the data access thread groups; and dispatching the target thread group to the load/store unit for execution.

Scheduling method and processing device for thread groups execution in a computing system

An analyzing method and an analyzing system for graphics process are provided. The analyzing method includes the following steps. A graphics application program is provided and a plurality of graphics parameters of the graphics application program are obtained. The graphics application program is classified to be at least one of a plurality of groups according to the graphics parameters. A plurality weighting coefficients are obtained. A total loading of a graphics processing unit for performing the graphics application program is calculated according to the weighting coefficients and the graphics parameters.

Analyzing method and analyzing system for graphics process of graphic application program

A NoC timing power estimating method includes: estimating a plurality of transmission timing of a plurality of transmission units of at least a packet, the transmission timing indicating respective time points at which the transmission units enter/leave a plurality of passing elements of the NoC; based on the transmission timing of the transmission units, estimating respective circuit states and respective power states of the passing elements of the NoC, the circuit state indicating an operation state of the passing element and the power state being related to the circuit state; and based on the power states of the passing elements of the NoC, estimating power consumption of the NoC.

NoC timing power estimating device and method thereof

A thermal simulation device is applied to a transaction-level designed chip which includes a plurality of intellectual properties. The thermal simulation device includes a plurality of thermal-aware transaction-level power model circuits, a simulator, a translator and a thermal emulator. The thermal-aware transaction-level power model circuits corresponds to the respective intellectual properties, and are configured to a corresponding power information for each of the intellectual properties, and dynamically adjusts the power information according to temperature information. The simulator is configured to generate the corresponding temperature information of the intellectual properties according to compatible information. The translator is configured to generate the compatible information which is compatible with the simulator. The thermal emulator is configured to trigger the simulator and transmit the temperature information to the intellectual properties.

Thermal simulation device and method

A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.

Data-processing apparatus and operation method thereof

A memory controlling device and method are disclosed for controlling a memory having a partial array self refresh (PASR) function and a plurality of memory segments. The memory controlling device comprises an address mapper, an address decoder, an address selector, and a PASR configuration register storing a PASR configuration. The address mapper converts an input address set into a mapped address set according to an address offset. The mapped address set comprises a plurality of consecutive mapped addresses or at least one mapped address within a limited range. The address decoder updates the PASR configuration during writing. The address selector generates an updated address set, which is used for setting at least one mode register of the memory, according to the PASR configuration register under a sleep-or-standby mode in order that the memory can self refresh at least one of the memory segments correspondingly.

Growing community of inventors

Hsinchu, Taiwan

Juin-Ming Lu