Semiconductor Manufacturing International (Shanghai) Corporation

Semiconductor Manufacturing International Corp.

Juilin Lu

YiQi Wang

Tzu-Yin Chiu

Aimei Lin

Jianxiang Cai

Jian Cai

Ty Chiu

Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.

SRAM memory cell and SRAM memory with conductive interconnect

A lateral double diffusion metal-oxide-semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate having a well region and a drain region in the well region. The LDMOS transistor also includes at least one drifting region in the well region and an annular source region in the drifting region surrounding the drain region. Further, the LDMOS transistor includes at least one annular isolation structure surrounding the drain region in the drifting region. Further, the LDMOS transistor also includes an annular gate dielectric layer on the well region and an annular gate on the annular gate dielectric layer.

Lateral double diffusion metal-oxide-semiconductor (LDMOS) transistors and fabrication method thereof

A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Methods for forming CMOS inverters

CMOS inverters and fabrication methods thereof

Semiconductor SRAM structures

Growing community of inventors

Shanghai, China

Juilin Lu