Realtek Semiconductor Inc.

Jui-Yuan Tsai

Chao-Cheng Lee

Wen-Chi Wang

Szu-Ping Chen

Yu-Pin Chou

Jin-Sheng Gong

Jui-Cheng Huang

Chang-Shun Liu

Chi-Feng Wang

Chia-Liang Chiang

Cheng-Jui Chen

Chi-Kung Kuan

Chao-Hsin Lu

Yueh-Hsing Huang

Yung-Hao Lin

A DC level redistribution method includes the steps of: receiving all positive signals and one negative signal of a plurality of pairs of differential signals; fixing a DC level of a positive signal of a designated pair of differential signals among a plurality of pairs of differential signals as a reference in order to adjust a DC level of a negative signal of the designated pair of differential signals for generating an adjusted negative signal; and taking the adjusted negative signal of the designated pair of differential signals as a reference in order to adjust DC levels of the positive signals of the other pairs of differential signals excluding the designated pair of differential signals. The DC redistribution method may be used in a display system.

Method and apparatus for DC level redistribution

The invention discloses an image processing system comprising a video source system, a transmission medium, and a television system. The image processing systems of the video source system and the television system are equipped with an additional digital-to-analog converter and an additional analog-to-digital converter.

Image processing system

A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.

Sync signal acquisition device

A video data source system includes a video encoder and an analog back end device. The analog back end device includes a digital to analog converter and a post-stage driving unit. The video data source system adds the post-stage driving unit into the analog back end device and strengthens its driving ability by the post-stage driving unit.

Video data source system

The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.

Image processing chip and related method for processing video

An image processing device is provided which comprises an input unit and an analog front end circuit with DC inputs. According to the invention, no capacitor is installed in the input unit and no clamper is installed in the AFE circuit with DC inputs. By appropriately selecting a comparing voltage and adding a level shifter or a compensation circuit, the invention can still generate an accurate digital signal.

Image processing device and method thereof

An analog front end device with temperature compensation is provided. The analog front end device comprises a bandgap voltage reference circuit, a clock generator, a temperature compensation circuit, one to three identical converting circuits and a Sync-on-Green circuit. The temperature compensation circuit is adapted to sense the temperature variations of the analog front end device and dynamically compensate the bandgap voltage reference circuit, the clock generator and the Sync-on-Green circuit as the temperature varies, which thereby controls the thermal drift in the analog front end device.

Analog front end device with temperature compensation

An analog front-end processing apparatus capable of sharing pins includes a plurality of positive pins, a negative pin, a plurality of positive clamping circuits, a negative clamping circuit, a plurality of sample and hold circuits and a plurality of adjusting circuits. The positive clamping circuits have positive signals fixed at their corresponding target positive voltages. The negative clamping circuit has a negative signal fixed at a first reference voltage. Each sample and hold circuit has a positive input terminal and a negative input terminal, wherein a voltage difference between the two input terminals is substantially equal to a voltage difference between the corresponding target positive voltage and the first reference voltage during a sample period, and a voltage difference between the two input terminals is equal to a voltage difference between the corresponding target negative voltage and a second reference voltage during a hold period.

Pin-sharing analog front-end processing apparatus and method for pin-sharing thereof

The invention discloses an analog front end device includes a calibration unit and at least a conversion circuit. The conversion circuit includes a clamper, a multiplexer, an voltage buffer and an analog to digital converter. The clamper receives an image signal and resets the DC voltage level of the image signal to generate a clamped signal. The multiplexer receives the clamped signal and a test signal and outputs the clamped signal or the test signal according to a selecting signal. The voltage buffer amplifies the clamped signal or the test signal to generate a buffer signal. The analog to digital converter converts the buffer signal into a digital signal. The calibration unit generates a gain correction value according to the test signal and calibrates the gain offset of the digital signal according to the gain correction value.

Analog front end device

An image processing device is provided which includes a pseudo differential analog front end circuit for receiving at least one image analog signal and generating at least one digital signal. The pseudo differential analog front end circuit includes at least a converting circuit, each of which includes a clamper, an input buffer and an analog-to-digital converter. All of the analog-to-digital converters receive a common comparing voltage if the number of the converting circuits is greater than one.

Pseudo-differential analog front end circuit and image processing device

A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.

Reference voltage generating circuit

An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.

Analog front-end circuit for digital displaying apparatus and control method thereof

An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

High voltage tolerance output stage

An image signal processing method adapted to an AFE device, which respectively generates first and second colors of digital signals according to first and second colors of analog signals. First, the first color of odd and even signals and the second color of odd and even signals are generated according to the first and second colors of analog signals, respectively. In a single channel mode, the first color of odd or even signal serves as the first color of digital signal for output, and the second color of odd or even signal serves as the second color of digital signal for output. In a dual channel mode, the first color of odd signal and second color of even signal are synchronously outputted, and the first color of even signal and second color of odd signal are also synchronously outputted. The first color of odd and even signals are combined to form the first color of digital signal, and the second color of odd and even signals are combined to form the second color of digital signal.

Image signal processing method and device

A reference voltage generating circuit includes: a first capacitor; a second capacitor; a reference voltage sampling capacitor; a first switch for alternatively coupling the second capacitor to a predetermined voltage to allow the second capacitor to sample the predetermined voltage; a second switch for alternatively coupling the second capacitor to the first capacitor to allow the second capacitor to redistribute charges with the first capacitor in order to generate the reference voltage; and a third switch for alternatively coupling the first capacitor to the reference voltage sampling capacitor to allow the reference voltage sampling capacitor to redistribute charges with the first capacitor in order to output the reference voltage.

Growing community of inventors

Tainan, Taiwan

Jui-Yuan Tsai