Taiwan Semiconductor Manufacturing Comp. Ltd.

Jui-Yu Chang

Syun-Ming Jang Jang

Tsu Shih

Chen-Hua Douglas Yu

Chung-Long Chang

Jeng-Horng Chen

Ying-Ho Chen

Kun-Pi Cheng

Tsu-Yu Chu

Chunshing Chen

Shyh-Chyi Wong

Chaochieh Tsai

A process for fabricating an RF type, MOSFET device, concentrating on reducing performance degrading gate resistance, has been developed. The process features formation of a stacked gate structure, comprised of a metal gate contact structure located directly overlying a portion of an underlying polysilicon gate structure, in a region in which the polysilicon gate structure is located on an active device region of a semiconductor substrate. Subsequent formation of an overlying metal interconnect structure, results in reduced gate resistance due to the direct vertical conductive path from the metal interconnect structure to the polysilicon gate structure, through the metal gate contact structure. A novel process sequence, requiring no photolithographic processing, is used to self-align the metal gate contact structure to the underlying polysilicon gate structure.

Self-aligned process for a stacked gate RF MOSFET device

A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

Method for photo alignment after CMP planarization

Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

Prevention of die loss to chemical mechanical polishing

A method of preserving alignment marks in integrated circuit substrates using shallow trench isolation after planarization using chemical mechanical polishing. A layer of silicon nitride is formed on the substrate and openings defining alignment trenches and isolation trenches are etched in the silicon nitride layer. Alignment trenches are formed in alignment regions of the substrate and isolation trenches are formed in the active region of the substrate during the same process step using the openings in the silicon nitride layer as a mask. A layer of dielectric is then deposited on the substrate filling the alignment trenches and the isolation trenches. The dielectric is then etched away from the alignment trenches and the substrate is planarized. After a layer of conducting material is deposited on the wafer the alignment trenches are preserved.

Method of photo alignment for shallow trench isolation with chemical

The present invention provides a method of removing an shallow trench isolation (STI) oxide layer 38 from over alignment marks 30. The invention has two major features: (1) A STI photoresist mask 42A that is used to etch Alignment area trenches 34 around alignment marks 30 and to etch STI trenches 35 in device areas 14; and (2) A 'reverse tone' STI photoresist mask 42B that is used to remove the isolation oxide 38 from over the alignment marks 30 and from over the active areas 37. The method begins by providing a substrate 10 having a device area 14, an alignment mark trench area 16; and an alignment mark area 18. A polish stop layer 20 22 is formed over the substrate 10. A trench isolation resist layer 42A is used to etch alignment area trenches 34 around the alignment marks 34 and STI trenches 35 in the device areas. A dielectric layer 38 is formed over the substrate. In a key step, the reverse tone trench isolation resist layer 42B is used to etch the first dielectric layer 38 from over the alignment marks 30 and the Active areas 27. Next, the remaining first dielectric layer 38 is chemical-mechanical polished thereby planarizing the first dielectric layer 38.

Method of photo alignment for shallow trench isolation

Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

A mask pattern and method are described for the recovery of alignment marks on an integrated circuit wafer without the use of additional masks. The mask pattern and method provide means to recover the alignment marks after forming a metal layer on a planarized inter-level dielectric layer. The pattern which conventional methods have placed on a separate mask is formed in the end regions of a mask used for forming a pattern on the active region of the wafer. In order to fit the pattern in the end regions of the mask the pattern is divided into two parts. When the pattern is used to expose a layer of photoresist two exposure steps are used.

Mask for recovering alignment marks after chemical mechanical polishing

A method of alignment for a chemical mechanical polishing includes previously patterning a primary zero alignment mark on a surface of a wafer. A first dielectric layer is deposited on the wafer for isolation. Then, an etching is used to etch the first dielectric layer using a photoresist as a mask. First conductive plugs are formed in the first dielectric layer. Next, a first conductive layer is formed on the surface of the first dielectric layer and on the tungsten plugs. Thus, the first non-zero alignment mark pattern is formed on the surface of the first conductive layer and aligned to the first conductive plugs. Next, a second non-zero alignment mark pattern is thus formed on the surface of a second conductive layer and aligned to the a second conductive plugs. By repeating the aforementioned method, odd non-zero alignment mark patterns will be formed over the first non-zero alignment mark pattern, and even non-zero alignment mark patterns will be formed over the second non-zero alignment mark pattern. Therefore, the present invention save space to put non-zero alignment marks in multilevel interconnection and planarization processes.

Alignment method for used in chemical mechanical polishing process

A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are followed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.

Method to protect alignment mark in CMP process

A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.

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Hsin-Chu, Taiwan

Jui-Yu Chang