Industrial Technology Research Institute

Taiwan Semiconductor Manufacturing Comp. Ltd.

Intellectual Property Innovation Corporation

Jui-Wen Yang

Tai-Jui Wang

Chieh-Wei Feng

Tzu-Yang Ting

Hsin-Cheng Lai

Yung-Hui Yeh

Chun-Hung Chu

Yu-Hua Chung

Hsiao-Chiang Yao

Chien-Hsun Chu

Shao-An Yan

Tzu-Hao Yu

The present disclosure provides a package structure, an antenna module, and a probe card. The package structure includes a connection member and a first redistribution structure disposed on the connection member. The connection member includes a conductive connector and an insulation layer surrounding the conductive connector. The first redistribution structure includes a first dielectric layer, and a first wiring pattern, and a first device. The first dielectric layer is disposed on the connection member. The first wiring pattern is disposed in the first dielectric layer. The first device is disposed above the first dielectric layer and is electrically connected to the conductive connector.

Package structure, antenna module and probe card

Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

Semiconductor package structure

A redistribution structure including a first redistribution layer is provided. The first redistribution layer includes a dielectric layer; at least one conductive structure located in the dielectric layer, wherein the at least one conductive structure has a width L; and at least one dummy structure located adjacent to the at least one conductive structure and located in the dielectric layer, and the at least one dummy structure has a width D, wherein there is a gap width S between the at least one dummy structure and the at least one conductive structure, and a degree of planarization DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1&#x2212;(h/T)]*100%, and h refers to a difference between a highest height and a lowest height of a top surface of the dielectric layer; and T refers to a thickness of the at least one conductive structure.

Redistribution structure and forming method thereof

A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.5&#xd7;10atoms/cm. A method of manufacturing the thin film transistor is also provided.

Thin film transistor and manufacturing method thereof

Growing community of inventors

Taipei, Taiwan

Jui-Wen Yang