Mediatek Corporation

Realtek Semiconductor Inc.

Jui-Tse Lin

Ta Hsing Liu

Yu-Hsun Chen

Yi-Hsin Yu

Li-Lien Lin

Tsung-Yen Tsai

Chang-Po Ma

Chih-Pao Lin

One packet output controller includes a scheduler and a dequeue device. The scheduler performs a single scheduler operation to schedule an output queue selected from a plurality of output queues associated with an egress port. The dequeue device dequeues multiple packets from the scheduled output queue decided by the single scheduler operation. Another packet output controller includes a scheduler and a dequeue device. The scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler performs a current scheduler operation, regardless of a status of a packet transmission of a scheduled output queue decided by a previous scheduler operation. The dequeue device dequeues at least one packet from the scheduled output queue decided by the current scheduler operation after the packet transmission of the scheduled output queue decided by the previous scheduler operation is complete.

Packet output controller and method for dequeuing multiple packets from one scheduled output queue and/or using over-scheduling to schedule output queues

A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

Scheduler for deciding final output queue by selecting one of multiple candidate output queues and related method

An output queue of a multi-plane network device includes a first processing circuit, a plurality of storage devices and a second processing circuit. The first processing circuit generates packet selection information based on an arrival sequence of a plurality of packets. The storage devices store a plurality of packet linked lists for the output queue. The second processing circuit dequeues a packet from the output queue by selecting a linked list entry from the packet linked lists according to the packet selection information.

Output queue of multi-plane network device and related method of managing output queue having multiple packet linked lists

The invention discloses a voltage regulating apparatus which includes: an output stage providing the apparatus with an output voltage and producing a partial voltage of the output voltage; an error amplifier coupled to the output stage and comparing the partial voltage with a reference to produce a first voltage; a PWM unit coupled to the error amplifier and comparing the first voltage with a voltage signal to produce second and third voltages; a selection unit coupled to the error amplifier and the PWM unit and outputting a fourth voltage equalling either the first or the second voltage; a first transistor coupled to the selection unit and receiving the fourth voltage and a DC voltage; and a second transistor coupled to the PWM unit, the first transistor, and a ground and receiving the third voltage; wherein a connection point of the first and second transistors is connected to the output stage.

Growing community of inventors

Hsinchu County, Taiwan

Jui-Tse Lin