United Microelectronics Corp.

Jui-Ting Li

Shu-Hua Kuo

Jiunn-Fu Liu

Yanan Mou

A circuit and method for measuring capacitance and capacitance mismatch of at least one capacitor pair are provided. The circuit includes a first switch, a second switch, a third switch and a P-type transistor. A terminal of the first switch is connected to a terminal of a first capacitor, and a terminal of the second switch is connected to a terminal of a second capacitor. A terminal of the third switch is connected to another terminal of the first capacitor and another terminal of the second capacitor, and a gate of the P-type transistor is connected to another terminal of the third switch. When the first, second and third switches are turned on, a capacitance of the first capacitor, a capacitance of the second capacitor, or a capacitance mismatch between the first and second capacitances is measured.

Method and circuit for measuring capacitance and capacitance mismatch

A method and apparatus for measuring a delay time is provided. First, a plurality of first/second phase signals, a first/second standard signal, and an inverse signal of the second standard signal are generated. The inverse signal of the second standard signal is applied to a second conductive line close to at least an adjacent conductive line. The first/second standard signal is applied to the first/second conductive line to obtain a first/second transmission signal. Then, the first/second transmission signal is sequentially sampled by the first/second phase signals to sequentially obtain a plurality of first/second sampling results. The first/second sampling results are sequentially identified by a first/second identifying level to obtain a first/second identification result. Accordingly, the delay time between the first and the second transmission signal may be obtained by comparing the different the second and the first identification result.

Growing community of inventors

Taipei County, Taiwan

Jui-Ting Li