Monolithic System Technology, Inc.

Monolithic Systems Technology, Inc.

Mosys, Inc.

Jui-Pin Tang

Wingyu Leung

A memory redundancy scheme is provided for re-routing data signal paths to disconnect defective memory blocks in a memory array. Each memory block is provided with a corresponding routing unit. Each routing unit is coupled to its corresponding memory block and at least one additional adjacent memory block. The routing units are configured to route data between functional memory blocks and a data bus. The routing units are controlled by configuration values stored in a shifter circuit, which extends through the routing units. To replace a defective memory block, the address of the defective memory block is identified. Configuration values are serially loaded into the shifter circuit, wherein the configuration values are selected in response to the address of the defective memory block. The configuration values cause the routing units to bypass the defective memory block, connect a redundant memory block, and shift connections in the memory blocks located between the redundant memory block and the defective memory block.

Method and apparatus for memory redundancy with no critical delay-path

A semi-conductor memory device having a wide write data bandwidth is provided with high speed read-write circuitry having data amplifiers that are activated to accelerate amplification of write data signals being driven by write data drivers onto data lines of the cell array of the device during memory write cycles, as well as activated to amplify read data signals on the data lines during memory read cycles. Moreover, the data amplifiers are activatedin a self-timed manner. In one embodiment, the device is further provided with a read data buffer that is constituted with a regenerative latch and an input stage, and a write data buffer having multiple entries. The input stage of the read data buffer isolates or couples the regenerative latch to the data lines depending on whether the data lines are in a pre-charged state or not. In one embodiment, the data amplifiers and the write drivers are further arranged to enable write data in the write buffer to be merged with the masked read data from the memory array when a read transaction hits the write buffer.

High-speed read-write circuitry for semi-conductor memory devices

A semi-conductor memory device having a wide write data bandwidth is provided with high speed read-write circuitry having data amplifiers that are activated to accelerate amplification of write data signals being driven by write data drivers onto data lines of the cell array of the device during memory write cycles, as well as activated to amplify read data signals on the data lines during memory read cycles. Moreover, the data amplifiers are activated in a self-timed manner. In one embodiment, the device is further provided with a read data buffer that is constituted with a regenerative latch and an input stage, and a write data buffer having multiple entries. The input stage of the read data buffer isolates or couples the regenerative latch to the data lines depending on whether the data lines are in a pre-charged state or not. In one embodiment, the data amplifiers and the write drivers are further arranged to enable write data in the write buffer to be merged with the masked read data from the memory array when a read transaction hits the write buffer.

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San Jose, CA, United States of America

Jui-Pin Tang