Taiwan Semiconductor Manufacturing Comp. Ltd.

Jui-Long Chen

Hui-yun Chao

Jong-I Mou

Chin-Hsiang Lin

Yen-Di Tsen

Chia-Tong Ho

Chun-Hsien Lin

Sheng-Yuan Lin

Tseng Chin Lo

Yi-Lii Huang

Chen-Liang Liao

Ta-Yung Lee

Po-An Chen

Chia-Yao Liang

Chien-Chih Liao

Kuo-Hsi Lee

Chia-Hung Huang

Sunny Wu

Po-Feng Tsai

Andy Tsen

A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.

Method of test probe alignment control

A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.

Semiconductor structure with resist protective oxide on isolation structure and method of manufacturing the same

A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.

A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

Systems and methods of automatically detecting failure patterns for semiconductor wafer fabrication processes

A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.

2D/3D analysis for abnormal tools and stages diagnosis

A system and method for manufacturing semiconductor devices is disclosed. An embodiment comprises using desired device parameters to choose an initial manufacturing recipe. Once chosen, the initial manufacturing recipe may be modified by determining and applying an offset adjustment based on previous manufacturing to tune the recipes for the particular equipment to be utilized in the manufacturing process.

Auto device skew manufacturing

System and method for data mining and feature tracking for fab-wide prediction and control are described. One embodiment is a system comprising a database for storing raw wafer manufacturing data; a data mining module for processing the raw wafer manufacturing data to select the best data therefrom in accordance with at least one of a plurality of knowledge-, statistic-, and effect-based processes; and a feature tracking module associated with the data mining module and comprising a self-learning model wherein a sensitivity of the self-learning model is dynamically tuned to meet real-time production circumstances, the feature tracking module receiving the selected data from the data mining module and generating prediction and control data therefrom; wherein the prediction and control data are used to control future processes in the wafer fabrication facility.

System and method for data mining and feature tracking for fab-wide prediction and control

A method for providing a bin ratio forecast at an early stage of integrated circuit device manufacturing processes is disclosed. The method comprises collecting historical data from one or more processed wafer lots; collect measurement data from one or more skew wafer lots; generating an estimated baseline distribution from the collected historical data and collected measurement data; generating an estimated performance distribution based on one or more specified parameters and the generated estimated baseline distribution; determining a bin ratio forecast by applying a bin definition and a yield degradation factor estimation to the generated estimated performance distribution; determining one or more production targets based on the bin ratio forecast; and processing one or more wafers based on the one or more determined production targets.

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Taichung, Taiwan

Jui-Long Chen