Taiwan Semiconductor Manufacturing Comp. Ltd.

Inventec Corp.

Micareo Taiwan Co., Ltd.

Vita Genomics, Inc.

University of Washington

Academia Sinica

Micareo Inc.

Jui-Lin Chen

Ping-Wei Wang

Feng-Ming Chang

Yu-Kuan Lin

Kian-Long Lim

Shih-Hao Lin

Chao-Yuan Chang

Hsin-Wen Su

Huai-Ying Huang

Chih-Hsuan Chen

Sheng Chiang Hung

Bwo-Ning Chen

Hui-Min Yu

Fu-Kai Yang

I-Wen Wu

Ting Fang

Pei-Jer Chen

Ding-Shinn Chen

Yuchi Hwang

Kuang-Den Chen

Ming-Yang Lai

Wei-Feng Fang

Daniel T Chiu

Chih-Chuan Yang

Chang-Ta Yang

Lien Jung Hung

Chenchen Jacob Wang

Ming-Shuan Li

Lie-Fen Shyur

Chih-Hsiang Huang

Ning-Sun Yang

Po-Sheng Lu

Mengxia Zhao

Perry G Schiro

Yuan-Hao Chang

Kuei-Ling Chen

Shang-Rong Li

Min-Pey Ding

Huai-Yang Huang

Chingwei Chang

Wen-Pi Chu

Shu-Ching Wang

Wan-Lin Yao

Eleanor S Shah

Wen-Feng Chung

Hui Min Yu

Shin-Hang Wang

Hong-Ling Wang

Chia-Ying Lee

Ju-Yu Tseng

Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.

Static random access memory with magnetic tunnel junction cells

Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

Method of forming a gate structure including semiconductor material implantation into dummy gate stack

A device includes a substrate, a contact, a first gate, a second gate, a dielectric feature between the gates, a via, and a conductive line. The gates are each adjacent the contact and aligned lengthwise with each other along a first direction. A first sidewall of the dielectric feature defines an end-wall of the first gate. A second sidewall of the dielectric feature defines an end-wall of the second gate. The conductive line extends along a second direction. A projection of the conductive line onto a top surface of the dielectric feature passes between the first and second sidewalls. The via interfaces with the contact along a second plane. The via has a first dimension on the second plane along the second direction; the contact has a second dimension on the second plane along the second direction. The first dimension is greater than the second dimension.

Integrated circuit device with reduced via resistance

A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (V) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.

Semiconductor devices with threshold voltage modulation layer

The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline 'WL' and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

SRAM devices with reduced coupling capacitance

Method of forming a gate structure

A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.

Magnetic device structure and methods of forming the same

An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.

Method of fabricating a semiconductor device including multiple contacts

A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

Source/drain contact having a protruding segment

The current disclosure is directed to a SRAM bit cell having a reduced coupling capacitance. In a vertical direction, a wordline 'WL' and a bitline 'BL' of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, the WL is vertically spaced apart from the BL with one or more metallization level that none of the WL or the BL is formed from. Connection island structures or jumper structures are provided to connect the upper one of the WL or the BL to the transistors of the SRAM cell.

Provided herein, among other aspects, are methods and apparatuses for analyzing particles in a sample. In some aspects, the particles can be analytes, cells, nucleic acids, or proteins and can be contacted with a tag, partitioned into aliquots, detected by a ranking device, and isolated. The methods and apparatuses provided herein may include a microfluidic chip. In some aspects, the methods and apparatuses may be used to quantify rare particles in a sample, such as cancer cells and other rare cells for disease diagnosis, prognosis, or treatment.

Particle separation systems and methods

The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.

Memory structure with doping-induced leakage paths

Growing community of inventors

Taipei, Taiwan

Jui-Lin Chen