Motorola Corporation

Jui-Kuo Juan

Robert E Stengel

David E Bockelman

Frederick L Martin

Frederick J Martin

David E Bockleman

A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element () and one or more secondary delay elements (). In one embodiment, a main delay line () is used to coarsely select a frequency output while a secondary delay element (), either passive or active, is used to increase the resolution of the primary delay line (). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line () as a driving signal for the passive secondary delay element () to provide the coarse adjustment and selecting an output from the secondary delay element () to provide the fine selection.

Cascaded delay locked loop circuit

A digital frequency synthesizer includes one or more reference clocks (A,A,A) optionally coupled through one or more pulse width reducers () to one or more main delay lines (B,B,B) that include a plurality of output taps (B-I,B-E). During at least certain periods of the reference clock () a plurality of the output taps are coupled to a common output (), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates () that are switched by gating pulses that are received from decoders () via gating signal delay lines ().

Method and apparatus for digital frequency synthesis

A direct digital synthesizer ( ) includes a first accumulator ( ) that acts as the frequency accumulator in order to generate the desired average frequency. A second accumulator ( ) acts to generate a phase correction at each overflow, with the input into the phase correction accumulator ( ) being a function of the input frequency. The clock signal of the phase correction accumulator ( ) is the overflow signal ( ) of the frequency accumulator ( ). With this configuration, the frequency accumulator ( ) generates the timing, and the phase correction accumulator ( ) generates the interpolation value. The use of the two accumulators ( ) as described, eliminates the need to use a multiplier in the design which is a high current consumption device.

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Coral Springs, FL, United States of America

Jui-Kuo Juan