Taiwan Semiconductor Manufacturing Comp. Ltd.

Jui-Jung Hsu

Chung-Hsing Wang

Kuo-Nan Yang

Chih-Hung Wu

Yu-Jen Chang

An integrated circuit (IC) design method is disclosed. The method includes: using a computer to perform synthesis upon a register transfer level (RTL) IC design to generate a gate level netlist; performing place and route (P&R) upon the gate level netlist to generate a layout; determining a sink current distribution information of the layout; and generating a voltage (IR) drop/electro-migration (EM) analysis result of the layout according to the sink current distribution information; wherein the layout includes a cell having a cell height that is N times higher than a single cell height, where N is an integer and greater than 1, and the cell corresponds to N power/ground (P/G) rail sets; wherein the sink current distribution information includes a proportion of a sink current flowing through each of the N power/ground (P/G) rail sets with respect to the cell when operated. Associated non-transitory computer-readable medium is also disclosed.

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Hsinchu, Taiwan

Jui-Jung Hsu