Storart Technology Co., Ltd.

Jui Hui Hung

Chih Nan Yen

Hou Yun Lee

Ming-Yi Chu

Hsueh Chih Yang

A method and a controller for recovering data in event of a program failure and a storage system using the method and the controller are disclosed. The controller includes main units of a parity generator, a volatile memory module and a processor. With a parity in the volatile memory module and successfully programmed sub-data, a program failed write data can be recovered and correctly programmed. The method of the present invention has advantages of saving use of storage resources and extending lifetime of the storage system than other methods for recovering data in event of a program failure.

Method and controller for recovering data in event of program failure and storage system using the same

A decoding algorithm with an enhanced parity check matrix and a re-encoding scheme for LDPC codes is disclosed. The decoding algorithm includes the steps of: providing the enhanced parity check matrix; receiving a message part of an original codeword encoded by a generator matrix from the enhanced parity check matrix; setting a LLR for each bit node of the enhanced parity check matrix; processing hard decision on the message part of the original codeword; encoding the message part of the original codeword by the generator matrix to generate a new codeword having a generated parity part; comparing the original parity part with the generated parity part to find out bits of difference; voting candidate error bits to choose the most probably erratic bits; modifying LLR of the chosen bits to have a modified codeword; and processing a conventional iterative decoding procedure on the modified codeword to have a processed codeword.

Decoding algorithm with enhanced parity check matrix and re-encoding scheme for LDPC code

An adaptive compression data storing method for non-volatile memories and a system using the method are disclosed. The system includes a host interface unit, a data compressor, a padding unit, a buffer, a combining unit, and a mapping table unit. By combining some compressed data in one page, the present invention can settle the problem that space for storing a compressed data that can not be utilized. Further, lifetime of non-volatile memories can be extended.

Adaptive compression data storing method for non-volatile memories and system using the same

A method for encoding multi-modes of BCH codes and an associated encoder is disclosed. The method has the steps of: building a number of encoding matrices; combining the encoding matrices with one side aligned to form a combined matrix; seeking common sub-expressions (CSEs) in the combined matrix, and encoding a message using the combined matrix.

Method for encoding multi-mode of BCH codes and encoder thereof

A method and decoder for early terminating decoding processes of serial concatenated coding are disclosed. The method includes the steps of providing a codeword, encoded by a first coding and a second coding sequentially; setting a maximum syndrome weight; decoding the second coding for the codeword by iterative calculations for syndromes; terminating decoding of the second coding if a number of the iterative calculations reaches a preset number or a syndrome weight of one iterative calculation is equal to or smaller than the maximum syndrome weight, otherwise repeating the decoding step and the terminating step; and decoding the first coding for the codeword.

Method for early terminating decoding processes of serial concatenated coding and decoder using the same

The present invention discloses a multi-code Chien's search circuit for BCH codes with various values of m in GF(2). The circuit includes: a combined matrix unit, a number of first multiplexers, a number of registers and a number of second multiplexers. By designing the Chien's search circuit having several Chien's search matrices, with peripheral components, it is able to achieve applications for different code rates, different code lengths and even different m in GF(2).

[object Object]

A simplified inversionless Berlekamp-Massey algorithm for binary BCH codes and circuit implementing the method are disclosed. The circuit includes a first register group, a second register group, a control element, an input element and a processing element. By breaking the completeness of math structure of the existing simplified inversionless Berlekamp-Massey algorithm, the amount of registers used can be reduced by two compared with conventional algorithm. Hardware complexity and operation time can be reduced.

Simplified inversionless berlekamp-massey algorithm for binary BCH code and circuit implementing therefor

A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost.

Serial multiply accumulator for galois field

A data format with ECC information for on-the-fly decoding during data transfer and method for forming the data format are disclosed. The method includes the steps of: dividing a parity check matrix having a message segment and a parity segment into a plurality of layers; choosing parity bit nodes in the parity segment of a first layer connected to check nodes; assembling the chosen parity bit nodes as a first parity segment and the rest parity bit nodes as a second parity segment; reallocating the parity check matrix so that the first parity segment is on the head of the message segment and the second parity segment is on the end of the message segment; forming a generating matrix according to the reallocated parity check matrix; and operating a message with the generating matrix to obtain the codeword.

Data format with ECC information for on-the-fly decoding during data transfer and method for forming the data format

An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of X, Xand Xaccording to p parallel computations and 2t syndromes; building up F; building up F'; building up F&#x2033;; building up matrix of [XF&#x2033;]; and designing a circuit which fulfills the operation of [XF&#x2033;].

Encoding and syndrome computing co-design circuit for BCH code and method for deciding the same

A method for shortening latency of Chien's search and related circuit are disclosed. The method includes the steps of: determining a shifted factor, p; receiving a BCH codeword; computing a syndrome from the BCH codeword; finding an error-location polynomial based on the syndrome; and processing Chien's search for the error-location polynomial to find out roots thereof. p is a number of successive zeroes from the first bit of the BCH codeword, the Chien's search starts iterative calculations by substituting a variable of the error-location polynomial with a nonzero element in Galois Field, GF(2), and the nonzero element ranges from &#x3b1;to &#x3b1;, wherein n is a codelength of the BCH codeword and equals 2&#x2212;1, and m is a positive integer.

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Hsinchu, Taiwan

Jui Hui Hung