Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Jui-Hsuan Feng

Ru-Gun Liu

Wen-Chun Huang

Cheng-Lung Tsai

Sheng-Wen Lin

Wen-Li Cheng

The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.

Pattern recognition for integrated circuit design

The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.

Mask error enhancement factor (MEEF) aware mask rule check (MRC)

The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a pattern, assigning target points to segments of the pattern, and producing first a simulated contour of the pattern based on the assigned target points. The method further includes reassigning the target points to the segments of the pattern based on the first simulated contour of the pattern; producing a second simulated contour of the pattern based on the reassigned target points, and after producing the second simulated contour of the pattern, producing a modified IC design layout.

Growing community of inventors

Lotung, Taiwan

Jui-Hsuan Feng