Nan Ya Technology Corporation

Jui-Hsiu Jao

Tsang-Po Yang

Yi-Ju Chen

Kai-Po Shang

Chun-Shun Huang

Ching-Chung Wang

Chih-Ying Chang

Wei-Li Lai

Yan-De Lin

Shian-Jyh Lin

Hsueh-Han Lu

Yi-Ting Tsai

Yin-Fa Chen

The present application provides a semiconductor device with a programmable feature. The semiconductor device includes a substrate, a conductive line, a conductive feature and a plurality of memory cells. The substrate includes a first island, a second island and an isolation structure, wherein the isolation structure is disposed between the first island and the second island. The first island has a first area, and the second island has a second area greater than the first area. The conductive line is disposed over the substrate. The conductive feature connects the conductive line to the second island. The plurality of memory cells are disposed in or on the first island.

Semiconductor device with programable feature

A fuse component and a semiconductor device and a semiconductor device having the fuse component are provided. The fuse component includes an active region having a surface, a first fuse dielectric layer extending from the surface of the active region into the active region, a first gate metal layer surrounded by the first fuse dielectric layer, a second fuse dielectric layer extending from the surface of the active region into the active region, and a second gate metal layer surrounded by the second fuse dielectric layer. The first gate metal layer is electrically connected with the second gate metal layer.

Fuse component and semiconductor device

A semiconductor wafer, a benchmark device embedded on a semiconductor wafer, and a method of operating a benchmark device embedded on a semiconductor wafer are provided. The semiconductor wafer includes a benchmark device disposed within a scribe line of the semiconductor wafer. The benchmark device includes a transistor, a diode, and a disconnecting switch electrically connected to the transistor and the diode. The disconnecting switch is configured to form a conductive path between the transistor and the diode at a first stage, and to electrically isolate the transistor from the diode at a second stage.

Benchmark device on a semiconductor wafer with fuse element

A method for detecting a memory chip includes the following steps coupling a detecting circuit to a first area and a second area of the memory chip, the second area is not overlapped with the first area; inputting a first detecting signal from the detecting circuit to the first area of the memory chip; burning out a cell of the detecting circuit; and inputting a second detecting signal from the detecting circuit to the second area of the memory chip.

Method for detecting memory chip

A semiconductor device with a fuse component is provided. The semiconductor device includes a substrate having an active region; a fuse dielectric layer disposed in the active region; and a gate metal layer disposed in the active region and surrounded by the fuse dielectric layer. The gate metal layer is configured to receive a voltage to change a resistivity between the gate metal layer and the active region.

Semiconductor device with fuse component

The present disclosure provides a method for manufacturing a fuse component having a three-dimensional (3D) structure. The method includes providing an active region, forming a first recess region and a second recess region in the active region, disposing a fuse dielectric material in the first recess region and the second recess region, and filling the first recess region and the second recess region with a gate metal material.

Method for manufacturing a fuse component

A fuse component, a semiconductor device, and a method of manufacturing a fuse component are provided. The fuse component includes an active region having a surface, a fuse dielectric layer extending from the surface of the active region into the active region, and a gate metal layer surrounded by the fuse dielectric layer.

Fuse component, semiconductor device, and method for manufacturing a fuse component

A method for activating a backup unit includes providing a fuse element connected to the backup unit. The fuse element includes an active area, which includes a source region and a drain region beside the source region, a gate region disposed on the active area, and a shallow trench isolation (STI) structure surrounding the active area. The method also includes applying a stress voltage on the drain region of the fuse element; accumulating electrons in a portion of the STI structure adjacent to the drain region; generating a conductive path through the drain region and the source region so that the fuse element is conductive; and activating the backup unit through the fuse element.

Method for activating backup unit through fuse element

The present disclosure provides a method of operating a benchmark device embedded on a semiconductor wafer. The method includes applying a first voltage to a first electrode of the benchmark device, and applying a second voltage to a second electrode of the benchmark device. The method further includes electrically isolating a first component of the benchmark device from a second component of the benchmark device through a disconnecting switch connected between the first component and the second component.

Method for operating a benchmark device on a semiconductor wafer with fuse element

A fuse element, a semiconductor device, and a method for activating a backup unit are provided. The fuse element includes an active area, which includes a source region and a drain region beside the source region, a gate region disposed on the active area, and a shallow trench isolation (STI) structure surrounding the active area. In addition, the drain region includes a terminal configured to receive a stress voltage, such that a conductive path is established through the drain region to the source region.

Fuse elements and semiconductor devices

A probe apparatus includes a chuck configured to support a wafer, a track surrounding the chuck, a tester disposed on the track and having a probe. The tester is configured to move around the wafer along a circumferential direction. The probe apparatus also includes a processing unit in communication with the tester and configured to control a movement of the tester.

Probe apparatus with a track

The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The plurality of unit cells are disposed in the test edge area, and the dummy area is free of the unit cells. A dimension of the test edge area in a top view is different from a dimension of the edge area in the top view.

Semiconductor structure with test structure

A probe apparatus and a wafer inspection method are provided. The probe apparatus includes a chuck configured to support a wafer, a track surrounding the chuck, a tester disposed on the track and having a probe, and a processing unit in communication with the tester and configured to move the tester circumferentially around the wafer such that the probe is moved from a first portion on the wafer to a second portion on the wafer.

Probe apparatus having a track and wafer inspection method using the same

The present application provides a memory test circuit and a device wafer including the memory test circuit. The memory test circuit is coupled to a memory array having intersecting first and second signal lines, and includes a fuse element and a transistor. The fuse element has a first terminal coupled to a first group of the first signal lines and a test voltage, and has a second terminal coupled to second and third groups of the first signal lines. The transistor has a source/drain terminal coupled to the second terminal of the fuse element and another source/drain terminal coupled to a reference voltage. The first group of the first signal lines are selectively coupled to the test voltage when the transistor is turned on, and all of the first signal lines are coupled to the test voltage when the transistor is kept off.

Memory test circuit and device wafer

The present disclosure provides a method for preparing a semiconductor device. The semiconductor device includes a substrate, a first region, a second region, a third region, a fourth region, a fifth region and a sixth region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. A plurality of second well regions are formed in the first region, the second region, the fourth region, the fifth region and the sixth region. A plurality of second well regions in the first region, the second region, the fourth region, the fifth region and the sixth region. The first well region, the second well region, the first type region and the second type region are formed by ion implantation.

Growing community of inventors

Taoyuan, Taiwan

Jui-Hsiu Jao