Taiwan Semiconductor Manufacturing Comp. Ltd.

Jui-Feng Jao

Sheng-Chen Wang

Tsung-Min Lin

Han-Chung Chen

Kern-Huat Ang

Fang-Chi Chien

Sheng-Chi Lin

Chiang-Yung Ku

Chai-Tak Teh

Min-Nin Yu

Gary Yang

Yuan-Shin Jing

Chai-Chen Liu

Jian-Liang Lin

Lung-Yin Tang

An insulator for an ion implantation source may provide electrical insulation between high voltage components and relatively lower voltage components of the ion implantation source. To reduce the likelihood of and/or prevent a leakage path forming along the insulator, the insulator may include an internal cavity having a back and forth pattern. The back and forth pattern of the internal cavity increases the mean free path of gas molecules in the ion implantation source and increases the surface area of the insulator that is not directly or outwardly exposed to the gas molecules. This results in a continuous film or coating being more difficult and/or less likely to form along the insulator, which extends the working time of the ion implantation source.

Insulator for an ion implantation source

A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces. The film layer, the polish stopping layer, and the conductive lines are polished down to the polish stopping layer overlying the first planar top surfaces to complete the polishing down of the conductive lines.

Nonvolatile semiconductor memory device

A method of fabricating a stacked dielectric layer for suppressing electrostatic charge buildup. First, a substrate having metal layers thereon is provided, with a plurality of gaps formed therebetween. Next, a dielectric layer is formed by simultaneous deposition and ion-bombardment, such that the dielectric layer covers the bottom dielectric liner and fills the gaps. Finally, a top dielectric liner is formed on the dielectric layer by deposition without ion-bombardment. Furthermore, the present invention provides another method to fabricate a stacked dielectric layer by performing a plasma treatment on the dielectric layer to suppress electrostatic charge buildup. As a result, the above-mentioned methods can efficiently avoid metal extrusion issues.

Fabrication of stacked dielectric layer for suppressing electrostatic charge buildup

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Toufen, Taiwan

Jui-Feng Jao