Taiwan Semiconductor Manufacturing Comp. Ltd.

Jui-Fen Chien

Hsiao-Kuan Wei

Hsien-Ming Lee

Hung-Wen Su

Chih-Chien Chi

Pei-Hsuan Lee

Hsin-Yun Hsu

Chin-You Hsu

Tsann Lin

Wei-Gang Chiu

Chih-Hsiang Fan

Pohan Kung

Hanwen Yeh

In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.

Magnetic tunnel junction devices

Provided is a semiconductor device including a first transistor of a first type comprising a first work function layer, the first work function layer comprising a first underlying layer; and a second transistor of the first type comprising a second work function layer, the second work function layer comprising a second underlying layer. The first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer. A method of manufacturing a gate structure for a semiconductor device is also provided.

Semiconductor device and method of manufacturing the same

Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Selective capping processes and structures formed thereby

Provided is a semiconductor device including a first n-type transistor comprising a first work function layer, the first work function layer comprising a first underlying layer; and a second n-type transistor comprising a second work function layer, the second work function layer comprising a second underlying layer. The first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer. A method of manufacturing a gate structure for a semiconductor device is also provided.

Magnetic tunnel junction device and method

A method for forming a semiconductor memory structure is provided. The method includes following operations. An interlayer is formed over a first ferromagnetic layer, wherein forming the interlayer includes following operations. A first metal film is formed by sputtering a first target material. A first oxygen treatment is conducted to the first metal film to form a first metal oxide film. A second metal oxide film is formed over the first metal oxide film by sputtering a second target material different from the first target material. A second metal film is formed by sputtering a third target material. A second oxygen treatment is conducted to the second metal film to form a third metal oxide film.

Method for forming semiconductor memory structure

Provided is a semiconductor device including a first n-type fin field effect transistor (FinFET) and a second n-type FinFET. The first FinFET includes a first work function layer. The first work function layer includes a first portion of a first layer. The second n-type FinFET includes a second work function layer. The second work function layer includes a second portion of the first layer and a first portion of a second layer underlying the second portion of the first layer. A thickness of the first work function layer is less than a thickness of the second work function layer. A method of manufacturing the semiconductor device is also provided.

Provided is a semiconductor device including a fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer is disposed over the second layer. The second layer includes a base material and a dopant doped in the base material. The dopant comprises Al, Ta, W, or a combination thereof. The first layer and the second layer comprise different materials. A method of manufacturing the semiconductor device is also provided.

Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.

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Taichung, Taiwan

Jui-Fen Chien