Win Semiconductors Corp.

Jui-Chieh Chiu

Chih-Wen Huang

Shao-Cheng Hsiao

Fan-Hsiu Huang

You-Cheng Lai

Po-Kie Tseng

Chen-Yang Hsieh

A gallium arsenide (GaAs) radio frequency (RF) circuit is disclosed. The GaAs RF circuit includes a power amplifier and a low noise amplifier; a first transmit/receive (TR) switch, coupled to the power amplifier and the low noise amplifier, wherein the first TR switch is fabricated by a pHEMT (Pseudomorphic High Electron Mobility Transistor) process; and a first active phase shifter, coupled to the power amplifier or the low noise amplifier, wherein the first active phase shifter is fabricated by an HBT (Heterojunction Bipolar Transistor) process; wherein the GaAs RF circuit is formed within a GaAs die.

Gallium arsenide radio frequency circuit and millimeter wave front-end module

A power flat no-lead (FN) package is provided. The power FN package includes a die paddle; a die, disposed on the die paddle, operating at a radio frequency; a first lead, disposed by a first side of the die paddle, configured to receive an input signal of the power FN package; and a capacitor, disposed on the first lead; wherein a lead width of the first lead is greater than a half of a first side length of the first side.

Power flat no-lead package

A bias compensation circuit, coupled to an amplifying transistor, is disclosed. The bias compensation circuit comprises a voltage locking circuit, comprising a first terminal and a second terminal, wherein the first terminal is coupled to a third terminal the amplifying transistor, and the second terminal is coupled to a control terminal of the amplifying transistor; and a first resistor, coupled to the first terminal of the voltage locking circuit; wherein when the voltage locking circuit is conducted, a voltage difference between the first terminal and the second terminal is substantially constant.

Bias compensation circuit and amplifying module

A radio frequency (RF) device includes a chip comprising a plurality of vias and at least a hot via; a signal lead and a ground lead disposed under a back side of the chip; and a signal metal sheet, a first ground metal sheet and a second ground metal sheet disposed on a top side of the chip. The signal metal sheet crosses over the first gap formed between the signal lead and the ground lead. The first ground metal sheet and the second ground metal sheet are coupled to the ground lead through the plurality of vias. The first ground metal sheet and the second ground metal sheet substantially surround the signal metal sheet.

Radio frequency device

A semiconductor device is disclosed. The semiconductor device includes a substrate; an active circuit portion, disposed on the substrate; a dielectric portion, disposed on the active circuit portion, wherein a hole is formed within the dielectric portion and the hole penetrates through the dielectric portion; and a radiating metal sheet, disposed on the dielectric portion; wherein the active circuit portion and the radiating metal sheet are coupled through the hole.

Semiconductor device with antenna integrated

A semiconductor device is disclosed. The semiconductor device includes a substrate; an active circuit portion including at least an active component and formed on a topside of the semiconductor device; and a radiating metal sheet formed on a backside of the semiconductor device. A hole is formed within the substrate and the hole penetrates through the substrate. The active circuit portion and the radiating metal sheet are coupled through the hole.

A transition structure disposed in a package is disclosed. The transition structure comprises a first ground lead and a second ground lead; and a signal lead, disposed between the first ground lead and the second ground lead, wherein the first ground lead and the second ground lead have an exterior edge and an interior edge, the signal lead is coupled to a metal line formed on a printed circuit board (PCB) and a signal terminal of the die within the package; wherein an exterior gap formed between the first ground lead and the second ground lead at the exterior edge is wider than an interior gap formed between the first ground lead and the second ground lead at the interior edge.

Transition structure and high-frequency package

A GaAs (Gallium Arsenide) cell is provided. The GaAs cell comprises at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction.

Gallium arsenide cell

A GaAs (Gallium Arsenide) cell is provided. The GaAs cell comprises a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, elongated on a first direction, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors; a plurality of second anchors; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing.

Gallium arsenide cell and logic circuit

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a winding structure formed on a top side the semiconductor substrate, wherein the winding structure comprises one or more metal lines winding with respect to a center of the winding structure; and a backside metal formed under a backside of the semiconductor substrate; wherein a hollow slot is formed within the backside metal, and a projection of the winding structure is within the hollow slot.

Semiconductor device with slotted backside metal for improving Q factor

A package structure is disclosed. The package structure includes at least a lead, for delivering at least a signal; at least a routing layer, connected to the at least a lead, where at least a first hole is formed through the at least a routing layer; a die, disposed on the at least a routing layer, where at least a second hole is formed through the die, and the die generates or receives the at least a signal; and a molding cap, for covering the at least a routing layer and the die; where the at least a signal is delivered through the at least a first hole and the at least a second hole.

Package structure and three dimensional package structure

A semiconductor package includes a die comprising at least a via and a least a hot via; a ground lead, formed directly under a back side of the die, contacting with the back side of the die, and directly connected to the a least a hot via and the at least a via of the die; a buffer layer, formed on the die, configured to absorb a stress applied to the die and prevent the die from damage; and a molding portion, formed on the die buffer layer.

Semiconductor package and manufacturing method

A biasing circuitry is disclosed. The biasing circuitry includes a biasing module, electrically connected to a power amplifier; and a control series, having an end electrically connected to a positive voltage, and another end electrically connected to the biasing module. The control series includes a switch unit, controlled by a control voltage to be on or off; and a voltage-drop unit, connected to the switch unit in series. The voltage-drop unit is configured to adjust a bias point of the power amplifier.

Biasing circuitry

A power amplifier (PA) has been disclosed for linearity improvement. The PA comprises at least an amplifying transistor and at least an auxiliary transistor. Each amplifying transistor of the at least an amplifying transistor includes a first terminal for receiving an input signal of the PA, a second terminal for delivering an output signal of the PA, and a third terminal. Each auxiliary transistor of the at least an auxiliary transistor includes a first terminal, a second terminal coupled to the second terminal of the at least an amplifying transistor, and a third terminal electrically connected to the first terminal of the at least an amplifying transistor.

Power amplifier

A low noise amplifier (LNA) has been disclosed for the noise and linearity performance improvement. The LNA includes an amplifying transistor and an auxiliary transistor. The amplifying transistor includes a first terminal for receiving an input signal of the LNA, a second terminal for outputting an output signal of the LNA, and a third terminal. The auxiliary transistor has a first terminal, a second terminal coupled to the second terminal of the amplifying transistor, and a third terminal electrically connected to the first terminal of the amplifying transistor.

Growing community of inventors

Taoyuan, Taiwan

Jui-Chieh Chiu