Sun Microsystems, Inc.

Jui-Cheng Su

Kevin B Normoyle

Rajasekhar Cherabuddi

Tzungren A Tzeng

Michael A Csoppenszky

Jaybharat Boddu

Alex S Han

Jayabharat Boddu

David A Penry

A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer. In one embodiment, the integrated I/O system contains a dedicated memory management unit including a translation lookaside buffer which converts I/O addresses to physical addresses for the processing core.

DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domains

A host includes a bus cache, a L1 cache and an enhanced snoop logic circuit to increase bandwidth of peripheral bus during a memory access transaction. When a device connected to the peripheral bus starts a memory read transaction, the host converts the virtual address of the memory read transaction to a physical address. The snoop logic circuit checks to see whether the physical address is in the bus cache and, if so, whether the data in the bus cache corresponding to address is valid. If there is a bus cache hit, the corresponding data is accessed from the bus cache and output onto the peripheral bus. However, if the snoop logic circuit does not find the physical address in the bus cache or finds that the data is invalid, the snoop logic circuit causes (1) the peripheral bus interface unit to perform a retry operation on the peripheral bus and (2) the cache controller to process a memory request to retrieve the requested data from the L1 cache, L2 cache (if any) or the main memory and store the requested data into the bus cache. In addition, when the device retries the memory read request, the bus cache will have the requested data so that the data can be immediately provided to the peripheral bus. Thus, in memory read transactions longer than a cache line, the data is provided on the peripheral bus in a pseudo-packet switched manner.

Cache subsystem with pseudo-packet switch

A system for maintaining completion order in a multiple bus system including a bridge that posts write data includes logic units for implementing a DRAIN/EMPTY protocol. A bridge logic unit asserts an EMPTY signal when the secondary posting buffers are empty. Interrupt processing is delayed until the EMPTY signal is asserted thereby assuring that all writes are completed. If an interrupt is received and the EMPTY signal is not asserted then a DRAIN signal is asserted while the EMPTY signal is not asserted. The bridge retries all upstream write requests until EMPTY is asserted.

Multiple bus bridge system for maintaining a complete order by delaying

Low-latency, high-throughput, integrated cache coherent I/O system for a

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Sunnyvale, CA, United States of America

Jui-Cheng Su