Samsung Electronics Co., Ltd.

Metisx Co., Ltd.

Xcena Inc.

Juhyun Kim

Dohun Kim

Jinyeong Kim

Sunwoo Kim

Minseob Kim

A test device includes semiconductor substrate, gate lines disposed on an upper surface of the semiconductor substrate and extending in a first direction parallel to the upper surface, a test element group including test transistors defined by the gate lines and by active regions extending in a second direction perpendicular to the first direction and intersecting the gate lines, and metal wirings disposed on the semiconductor substrate and electrically connected to the active regions and/or the gate lines, and a test circuit electrically connected to the metal wirings and configured to measure resistance of the test transistors. The gate lines include first gate lines and second gate lines disposed alternately, with the spacing between first gate lines and second gate lines alternating between a first distance and a second distance greater than the first distance.

Test element group and test device including the same

Provided is a method for managing an adaptive cache pool, which is performed by one or more processors, and includes receiving monitoring information on a cache memory divided into a plurality of cache pools, and adjusting a cache region associated with at least one of the plurality of cache pools based on the monitoring information.

Method and apparatus for adaptively managing cache pool

Growing community of inventors

YONGIN-SI, South Korea

Juhyun Kim